Staggered Bonding Pad Layout for High-Speed IC Packaging

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Solution Overview

Problem

Conventional wire-bonding methods fail to adequately accommodate high-speed differential pairs of signals within smaller semiconductor package sizes, requiring larger die sizes and inadequate close coupling between wire bonds to meet tightening production parameters.

Innovation Solution

A mixed wire bonding and staggered bonding pad placement method is employed, where pairs of bonding pads are arranged in double rows with staggered configurations and varying wire diameters to optimize mutual and loop inductance, allowing for improved signal transmission without increasing die size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional single-row wire-bonding methods are used, then the manufacturing process is simple, but the package size must be enlarged to accommodate high-speed differential pairs with adequate coupling

Engineering Contradiction:
Improvewire-bonding process simplicityVSAvoidsemiconductor die size
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent transitions from a single-row linear arrangement of bonding pads to a two-dimensional staggered grid pattern. This dimensional change allows bonding pads to be distributed across multiple rows and columns, enabling high-speed differential pairs to achieve close coupling without requiring a larger die area. The staggered arrangement optimizes spatial utilization and enables adequate signal coupling within the same package footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The bonding pad array is segmented into multiple distinct rows and columns rather than using a single continuous row. This segmentation allows different regions of the die to be optimized for different functions - some areas for high-speed differential pairs requiring close coupling, and other areas for standard I/O signals. The segmented structure enables independent optimization of signal integrity and package density.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If the quantity of bonding pads is increased to accommodate more I/O signals, then the signal transmission capability is improved, but the die size must be enlarged

Engineering Contradiction:
Improvenumber of bonding padsVSAvoidsemiconductor die size
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The staggered multi-row bonding pad configuration enables a nested-like arrangement where bonding pads are distributed across multiple hierarchical levels (rows and columns). This allows the die to accommodate a higher density of bonding pads by utilizing two-dimensional space efficiently, rather than simply extending in one dimension. The nested structure maximizes the number of I/O signals that can be supported within a fixed die area.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Reliability

If longer rows of bond pads are used to meet signal transmission requirements, then the high-speed signal coupling is improved, but the die size increases

Engineering Contradiction:
Improvesignal transmission qualityVSAvoidbond pad row length
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent resolves the need for long bond pad rows by transitioning to a multi-row staggered configuration. Instead of extending the bond pad arrangement in a single long row, the solution distributes bonding pads across multiple shorter rows in a staggered pattern. This achieves the same signal coupling effectiveness for high-speed differential pairs while maintaining a compact die footprint, as the coupling is achieved through spatial proximity in two dimensions rather than linear distance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9184151B2Mixed wire bonding profile and pad-layout configurations in IC packaging processes for high-speed electronic devices
Publication Date: 2015.11.10 CYPRESS SEMICONDUCTOR CORP
  • US9184151B2 patent drawing
  • US9184151B2 patent drawing
  • US9184151B2 patent drawing

AI summary

A method and apparatus for mixed wire bonding and staggered bonding pad placement. A first plurality of bonding pads is arranged on a semiconductor device. A second plurality of bonding pads is also arranged on the semiconductor device. The bonding pads of the second plurality of bonding pads are arranged in a staggered pattern, such that the first and second pluralities of bonding pads form one of a plurality of double rows of bonding pads on the semiconductor device.