Staggered Conductive Vias in Semiconductor Package
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Solution Overview
Problem
Semiconductor packaging technologies face challenges in protecting conductive features from cracks during processes like bonding and soldering while maintaining miniaturization and simplicity, as the reduced dimensions of redistribution layers make them more susceptible to damage.
Innovation Solution
A semiconductor package design featuring a face-to-face configuration of dies with a redistribution structure having shifted conductive vias, which are laterally offset to reduce stress and enhance reliability, and an insulating encapsulation that separates and protects the dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the dimension of conductive features of redistribution layer is reduced for miniaturization, then the size of semiconductor package is reduced, but the conductive features become more sensitive to cracks when subjecting to forces
Solution Approach 1:
The patent introduces a lateral offset between conductive vias at different levels of the redistribution structure, transitioning from a vertical alignment problem to a three-dimensional staggered configuration. This dimensional approach distributes stress across multiple lateral positions, preventing crack propagation that would occur in vertically aligned via structures under miniaturized dimensions.
Solution Approach 2:
The patent employs asymmetric positioning of conductive vias where the first conductive via at the first level is laterally offset from the second conductive via at the second level. This asymmetric, staggered arrangement breaks the vertical symmetry that would concentrate stress, thereby reducing crack sensitivity while maintaining the miniaturized package size.
2Ease of manufacture
If conventional aligned conductive via structure is used, then manufacturing is simpler, but stress concentration occurs during bonding and soldering processes
Solution Approach 1:
The patent resolves stress concentration by moving from a two-dimensional vertical alignment to a three-dimensional staggered configuration. The lateral offset between vias at different levels creates a more distributed stress field that accommodates bonding and soldering forces without concentrating stress at single points.
3Reliability
If vertically aligned conductive vias are used in redistribution structure, then electrical connection is more direct, but cracks and defects occur during processing and operation
Solution Approach 1:
The patent uses asymmetric, staggered positioning of conductive vias to eliminate the vertical alignment that causes crack concentration. The lateral offset creates an asymmetric stress distribution that prevents crack initiation and propagation, thereby eliminating defects while maintaining reliable electrical connection through the staggered via pathway.
Data Source
AI summary
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first dies, an insulating encapsulation laterally encapsulating the first dies, a second die disposed over the portion of the insulating encapsulation and at least partially overlapping the first dies, and a redistribution structure disposed on the insulating encapsulation and electrically connected to the first dies and the second die. A second active surface of the second die faces toward first active surfaces of the first dies. The redistribution structure includes a first conductive via disposed proximal to the first dies, and a second conductive via disposed proximal to the second die. The first and second conductive vias are electrically coupled and disposed in a region of the redistribution structure between the second die and one of the first dies. The first conductive via is staggered from the second conductive via by a lateral offset.