Staggered Lead Frame Power Semiconductor Package Thermal Dissipation
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Solution Overview
Problem
Conventional power semiconductor packages face challenges in achieving both compact size and effective thermal dissipation, with complex manufacturing processes and precise thickness control requirements, leading to poor heat dissipation and increased costs.
Innovation Solution
A lead frame structure with a staggered design and a thin metal layer is used, featuring etched contact holes and openings for solder balls, allowing for a thinner and more compact package with improved thermal dissipation by exposing metal bumps for better heat transfer, and a molding process that reduces overall package size and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the thickness of the MOSFET is precisely controlled within a very narrow range to satisfy the coplanar condition, then the coplanarity of source/gate electrodes and leads is improved, but the manufacturing complexity and cost increase significantly
Solution Approach 1:
The lead frame is divided into two distinct sections: an upper section with leads and a lower section with a die pad. This segmentation allows each section to be independently designed and manufactured with appropriate thicknesses, eliminating the need for precise coplanarity control of the entire structure. The upper and lower sections are then joined through molding, achieving the desired coplanar configuration without narrow tolerance requirements.
Solution Approach 2:
The invention transitions from a single-plane coplanarity requirement to a multi-dimensional stacked structure. By arranging leads and die pad in different vertical levels (upper and lower sections) and joining them through molding, the design achieves functional coplanarity of electrodes and leads while allowing greater thickness variation in each component.
2Reliability
If leads are positioned on opposite sides of the chip to achieve electrical connection, then the electrical functionality is satisfied, but the package size increases
Solution Approach 1:
The upper section containing the leads and the lower section containing the die pad are merged into a single integrated lead frame structure through the molding process. This consolidation allows leads to be positioned on opposite sides of the chip while maintaining a compact overall package size, as the two sections occupy overlapping vertical space rather than extending horizontally in opposite directions.
3Reliability
If conventional molding processes are used to cover the MOSFET completely, then the protection and encapsulation are improved, but the package thickness increases and thermal dissipation performance deteriorates
Solution Approach 1:
The molding process is modified to extract or leave exposed the upper section of the lead frame containing the leads, rather than completely covering it. This selective exposure allows the molding material to protect the lower section and MOSFET while maintaining thin overall package thickness and enabling direct thermal pathways from the die pad to the leads for improved heat dissipation.
Data Source
AI summary
An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.