Staggered LED Chip Arrangement for High-Voltage Light-Emitting Device
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Solution Overview
Problem
Current light-emitting diode (LED) chip arrangements in high-voltage devices suffer from low luminous efficiency due to side wall shielding, resulting in wasted light output and inefficient lighting, as chips are typically aligned in a matrix configuration where side emissions are obstructed by adjacent chips.
Innovation Solution
The implementation of an interleaved or staggered arrangement of LED chips on a substrate, with 18 to 25 chips connected in series, allowing for enhanced light output from both top and side surfaces, and the use of a current blocking layer to direct current away from the P-type electrode, improving light emission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If light-emitting diode chips are arranged side by side in a matrix configuration on a substrate, then the device structure is simple and manufacturing is easy, but light output from side walls is shielded by adjacent chips resulting in low lighting efficiency
Solution Approach 1:
The patent applies asymmetry by transitioning from a symmetric matrix arrangement to an asymmetric interleaved/staggered arrangement where chips are offset from each other. This asymmetric positioning eliminates the shielding effect that occurs in symmetric matrix configurations, allowing side wall light emission while maintaining manufacturing simplicity.
Solution Approach 2:
The patent utilizes dimensional change by arranging chips in an interleaved pattern across multiple rows and columns with offset positioning. This two-dimensional staggered arrangement allows light to escape from side walls that would otherwise be blocked in a flat matrix configuration, effectively using spatial dimensionality to resolve the shielding problem.
2Area of moving object
If a large number of light-emitting diode chips are arranged on a substrate to form a light-emitting matrix, then the light-output area increases, but cooling problems become more frequent and light-output efficiency is reduced due to side wall shielding
Solution Approach 1:
The asymmetric interleaved arrangement allows chips to be positioned such that their side walls are exposed rather than shielded. This maintains large light-output area while improving efficiency by enabling light emission from previously blocked side surfaces.
Solution Approach 2:
By arranging chips in a staggered two-dimensional pattern rather than a flat matrix, the patent creates vertical and diagonal spacing that exposes side wall surfaces. This dimensional reorganization allows simultaneous achievement of large light-output area and high light-output efficiency.
3Device complexity
If light-emitting diode chips are arranged in a matrix configuration, then the device structure is straightforward, but most side wall light emission is blocked by adjacent chips resulting in wasted light output
Solution Approach 1:
The patent introduces asymmetry in chip positioning to eliminate the energy waste caused by symmetric matrix shielding. The interleaved offset arrangement allows side wall light to escape, converting what would be wasted energy into useful light output while adding minimal complexity to the device structure.
Solution Approach 2:
The patent converts the harmful shielding effect into a beneficial exposure effect. By staggering chip positions, the arrangement that would normally block light (adjacent chips) instead becomes part of a pattern that exposes side walls, transforming the shielding harm into light-emitting benefit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly enhances lighting efficiency by utilizing 60% to 80% of the substrate area for top surface emissions and optimizing side wall emissions, while maintaining appropriate voltage ranges and production costs.
Implementation Method 1
light-emitting diode chips have an interleaved or staggered arrangement, allowing for enhanced light output from both top and side surfaces
Data Source
AI summary
The present invention relates to a high-voltage light-emitting device suitable for light-emitting diode chip array module. The device comprises a set of light emitting diode chips, about 18˜25 chips, deposited on a substrate by using a non-matrix arrangement. Through the adjustments, the high-voltage light-emitting device of the present invention has optimized luminous efficiency.