Staggered Memory Testing Circuit Voltage Drop Control
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Solution Overview
Problem
Existing testing technologies face challenges in efficiently testing multiple memory circuits without causing excessive instantaneous voltage drops, either by increasing circuit area or testing time when using a single testing circuit, or by dividing memory circuits into groups for time division testing.
Innovation Solution
A single testing circuit is used to perform read/write operations on multiple memory circuits with staggered starting time points, controlled by a memory access controller that includes enabling signal generators, address generators, and offset circuits to manage the read/write operations across memory circuits with varying storage capacities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single testing circuit is used to test multiple memory circuits simultaneously, then the circuit area is reduced, but excessive instantaneous voltage drop occurs
Solution Approach 1:
The patent applies periodic action by implementing time-division multiplexed testing where the single testing circuit sequentially tests different memory circuits at different time intervals. The testing circuit performs read/write operations on memory circuits in a staggered manner, with each memory circuit having a different read/write starting time point, thereby distributing the instantaneous current demand over time and avoiding excessive voltage drop while maintaining compact circuit area
Solution Approach 2:
The patent implements dynamics by making the testing circuit's operation mode adjustable between simultaneous and sequential testing based on system requirements. The controller dynamically adjusts the timing parameters and read/write starting time points of different memory circuits, allowing flexible optimization between testing speed and power consumption without fixed architectural constraints
2Object-affected harmful factors
If multiple testing circuits are used to test multiple memory circuits simultaneously, then the instantaneous voltage drop is avoided, but the circuit area increases
Solution Approach 1:
The patent applies universality by designing a single testing circuit that can perform multiple testing functions on different memory circuits through time-division multiplexing. The same testing circuit is reused across multiple testing cycles with different configuration parameters, eliminating the need for dedicated testing circuits for each memory circuit while maintaining comprehensive testing coverage and avoiding excessive voltage drop
3Object-affected harmful factors
If memory circuits are divided into groups for time division testing, then the instantaneous voltage drop is avoided, but the testing time increases
Solution Approach 1:
The patent implements dynamics by making the testing sequence and time intervals adjustable based on system requirements. The controller can dynamically optimize the read/write starting time points and testing schedules for different memory circuits, allowing flexible balancing between avoiding voltage drop and minimizing testing time without fixed group divisions
Solution Approach 2:
The patent applies parameter changes by adjusting timing parameters, read/write starting time points, and testing sequence dynamically. The system can modify operational parameters such as the time intervals between testing different memory circuits to optimize the balance between power consumption and testing efficiency based on specific system requirements
Data Source
AI summary
A testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation. The testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other.