Vertically Staggered MTJ Memory Array for Higher BEOL Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in increasing the density and complexity of integrated circuits, particularly in the manufacturing of magnetic tunnel junctions (MTJs) for memory devices, where scaling down leads to increased complexity and requires innovative methods to enhance memory array formation without occupying excessive back-end-of-line (BEOL) area.
Innovation Solution
The method involves forming a memory array with different leveled magnetic tunnel junctions (MTJs) using a specific process that includes forming seed layers, pinned layers, spacer layers, reference layers, tunnel barrier layers, and free layers, followed by patterning and encapsulation, allowing for the creation of high-density memory devices with reduced lateral spacing between MTJ stacks, thereby saving BEOL area and enabling efficient spin-transfer torque (STT) MRAM or other memory types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar MTJ arrays are used, then manufacturing process is simpler, but memory density and functional density are limited
Solution Approach 1:
The patent transitions from a two-dimensional planar MTJ array to a three-dimensional vertically-staggered configuration. Multiple MTJ stacks are positioned at different vertical levels (e.g., first MTJ stacks at a first level, second MTJ stacks at a second level), enabling higher memory density without proportionally increasing lateral footprint or manufacturing complexity
Solution Approach 2:
The memory array is segmented into multiple independently-formed MTJ stacks at different vertical levels. Each level can be formed through separate processing steps, allowing modular manufacturing that reduces overall complexity while increasing total memory capacity
2Quantity of substance
If minimum feature size is decreased to increase functional density, then more devices fit per chip area, but IC processing and manufacturing complexity increases
Solution Approach 1:
Instead of continuously scaling down lateral feature sizes, the patent exploits the vertical dimension by stacking MTJ structures at different levels. This achieves increased functional density while avoiding the manufacturing complexity associated with sub-lithographic scaling
Solution Approach 2:
Multiple MTJ stacks are nested vertically within the same lateral footprint area. The staggered configuration allows MTJ stacks at different levels to occupy overlapping horizontal spaces, effectively nesting memory elements in the vertical dimension to increase density without lateral scaling
3Area of stationary object
If MTJ stacks are placed closer together to reduce layout area, then memory density increases, but manufacturing precision requirements increase
Solution Approach 1:
By utilizing vertical staggering, the patent reduces lateral spacing requirements between MTJ stacks. The offset vertical positions allow closer lateral placement without direct interference, reducing layout area while maintaining manufacturable precision tolerances
Solution Approach 2:
The patent applies different vertical positioning (local quality) to different MTJ stacks within the same array. First MTJ stacks are positioned at a first vertical level while second MTJ stacks are positioned at a second vertical level, allowing optimized lateral spacing that reduces overall layout area while maintaining manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-density integrated memory devices with reduced layout area, allowing for closer placement of memory cells and improved manufacturing efficiency by vertically staggering MTJ stacks, which reduces the layout area and enhances design flexibility.
Implementation Method 1
An MTJ is a device that changes its resistive state based on the state of magnetic materials within the device
Implementation Method 2
The MTJ involves spin electronics, which combines semiconductor technology and magnetic materials and devices. The spin polarization of electrons, rather than the charge of the electrons, is used to indicate the state of '1' or '0'
Data Source
AI summary
A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.