Staggered-Tuned Power Amplifier for Wider Bandwidth and Flatness
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Solution Overview
Problem
Designing high-power power amplifiers on advanced process nodes (such as 65 nm or below) is challenging due to poor tolerance of voltage swing and current swing, leading to limited bandwidth and efficiency, and high cost with many inductors in existing architectures.
Innovation Solution
A power amplifier architecture featuring a staggered tuning circuit and a power combining circuit with two differential amplifiers, where the center frequencies of parallel resonance networks are set to different values through a setting relationship, allowing for cascaded tuning and improved bandwidth, reducing the usable area and enhancing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If many inductors are used in existing amplifier architectures, then gain and bandwidth can be achieved, but the usable area increases and cost increases
Solution Approach 1:
The patent transforms the traditional inductor-based matching networks into capacitor-based resonant circuits by changing the fundamental circuit parameters. This substitution of components (inductors to capacitors) allows achieving the same bandwidth performance with significantly reduced area, as capacitors occupy less chip area than inductors in advanced CMOS processes
Solution Approach 2:
The patent replaces the mechanical/physical inductor structures with electrical capacitor-based resonant systems. By using LC resonant circuits where capacitors play the dominant role, the system achieves equivalent electrical performance (bandwidth, gain) without the area penalty of traditional inductor implementations
2Power
If all stages are tuned at the same frequency point, then gain and band selectivity are optimized, but the design space becomes narrower and bandwidth is limited
Solution Approach 1:
The patent implements dynamic frequency distribution across different amplifier stages through staggered tuning. Each stage operates at a different center frequency (f0, f0+Δf, f0-Δf), creating a distributed frequency response that dynamically expands the overall bandwidth while maintaining gain performance through the combined effect of all stages
Solution Approach 2:
The patent segments the single frequency-tuning function into multiple independent tuning functions across different stages. Each amplifier stage has its own tuned LC circuit with a distinct center frequency, allowing independent optimization of each stage's contribution to the overall frequency response, thereby expanding total bandwidth
3Loss of energy
If gain allocation and bias conditions are optimized for efficiency, then power efficiency improves, but bandwidth is severely limited
Solution Approach 1:
The patent changes the frequency distribution parameter across stages from uniform (same center frequency) to staggered (different center frequencies). This parameter change allows the system to simultaneously maintain efficient bias conditions in each stage while achieving expanded bandwidth through the cumulative frequency response of all stages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture improves in-band signal quality, band filtering, and reliability, making it suitable for carrier aggregation communication, while maintaining good flatness within the band and reducing the number of transformers needed.
Implementation Method 1
set center frequencies of parallel resonance networks of different stages to be different values through a setting relationship
Data Source
AI summary
The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency point 1 less than the design frequency point and frequency point 2 greater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.