Stair-Form Stacked Semiconductor Package Wire Bonding Protection
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Solution Overview
Problem
The challenge in stacking semiconductor chips is the potential damage caused by excessive impact during wire bonding, particularly when the chips are thin, as they are only several tens of micrometers to several hundreds of micrometers thick, leading to issues with bonding pads and substrate contact pads.
Innovation Solution
A stacked semiconductor package design where semiconductor chips are stacked in a stair form with adhesive members of varying thicknesses to support each other, preventing damage during wire bonding by aligning the uppermost and lowermost chips and using conductive wires to couple edge bonding pads with substrate contact pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked with thin thickness to improve integration density, then data capacity and processing speed are improved, but the chips become susceptible to damage from excessive impact during wire bonding
Solution Approach 1:
The patent transitions from planar stacking to three-dimensional stair-shaped stacking, where chips are arranged in multiple levels with offset positions. This dimensional change allows the uppermost chip to be positioned higher than lower chips, creating a stepped configuration that reduces impact during wire bonding while maintaining high integration density through vertical space utilization.
Solution Approach 2:
The patent applies adhesive members with varying thicknesses between stacked chips, with the thickest adhesive member positioned under the uppermost chip. This beforehand cushioning provides enhanced protection to the most vulnerable chip during wire bonding operations, absorbing impact forces before they reach the thin semiconductor substrate.
2Productivity
If wire bonding is performed on stacked chips to electrically couple bonding pads, then data capacity and processing speed are improved, but excessive impact from the capillary damages the thin semiconductor chips
Solution Approach 1:
By arranging chips in a stair-shaped configuration with vertical offset, the patent creates spatial separation between the wire bonding operation zone and the vulnerable chip surfaces. The uppermost chip is positioned at a higher elevation, reducing the direct impact force from the capillary during wire bonding while maintaining electrical connectivity through conductive wires.
Solution Approach 2:
The adhesive members serve as intermediary elements between the stacked chips, with varying thicknesses providing differential cushioning. The thickest adhesive member is strategically placed under the uppermost chip to absorb and distribute impact forces from wire bonding operations, protecting the thin semiconductor substrate while allowing electrical coupling to proceed.
3Ease of manufacture
If multiple adhesive members with uniform thickness are used to stack chips, then manufacturing is simplified, but the uppermost chip cannot be adequately protected from impact during wire bonding
Solution Approach 1:
The patent applies adhesive members with non-uniform thicknesses, specifically making the adhesive member under the uppermost chip thicker than those between other stacked chips. This local quality variation provides enhanced protection precisely where it is most needed - at the position most susceptible to impact during wire bonding - while maintaining relatively simple manufacturing processes for the overall stacking operation.
Data Source
AI summary
A stacked semiconductor package includes a substrate having first and second contact pads. A first stacked package group is disposed on the substrate, and the first stacked package group includes first semiconductor chips stacked in a stair form to expose first edge bonding pads. First conductive wires are used to electrically couple the first edge bonding pads and the first contact pads. An adhesive member is disposed on the uppermost first semiconductor chip, and a second stacked package group is disposed on the adhesive member. The second stacked package group includes second semiconductor chips that are stacked in a stair form to expose second edge bonding pads. When the second stacked package group is disposed on the adhesive member, the bottommost second semiconductor chips is aligned with the uppermost first semiconductor chip. Second conductive wires are used to electrically couple the second edge bonding pads and the second contact pads.