Staircase Contact Insulating Layer Oxygen Gradient
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Solution Overview
Problem
Current semiconductor manufacturing methods for three-dimensional memory devices face challenges in efficiently connecting electrode layers to control circuits due to limitations in staircase-shaped contact structures and electrical isolation, leading to issues with chip size and layout flexibility.
Innovation Solution
A semiconductor device is designed with a stacked body featuring electrode layers and insulating layers, where the insulating layer has a non-uniform oxygen composition ratio, allowing for a staircase configuration that supports efficient electrical connections and reduces chip size by controlling the thickness and composition of the insulating layer to minimize side etching during etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a staircase-shaped contact structure is used to connect multiple electrode layers to control circuits, then electrical connections are established, but side etching and bowed configurations occur during etching processes
Solution Approach 1:
The insulating layer is designed with non-uniform thickness, having a first thickness in a first region and a second thickness greater than the first thickness in a second region. This local variation in thickness provides enhanced etching protection precisely where the staircase structure is most vulnerable, suppressing side etching and bowed configurations while maintaining electrical connection reliability.
Solution Approach 2:
The insulating layer with non-uniform thickness is formed before the etching process to preemptively protect the staircase structure. The thicker portion in the second region is prepared in advance to counteract the side etching that will occur during subsequent etching steps, preventing bowed configurations before they happen.
2Manufacturing precision
If the insulating layer thickness is increased to suppress side etching, then etching protection is improved, but chip size increases
Solution Approach 1:
Instead of uniformly increasing the insulating layer thickness across the entire chip, the invention applies increased thickness locally only in the second region where it is most needed for etching protection. This targeted approach suppresses side etching effectively while minimizing the overall chip area increase.
Solution Approach 2:
The insulating layer thickness is increased partially (only in the second region) rather than excessively across the entire structure. This partial action provides sufficient etching protection where the staircase configuration is most vulnerable without unnecessarily increasing the chip size in regions where additional thickness is not required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables reliable electrical connections and reduces chip size by suppressing side etching and bowed configurations, improving the layout flexibility and manufacturing efficiency of three-dimensional memory devices.
Implementation Method 1
The insulating layer includes an upper layer portion and a lower layer portion. An oxygen composition ratio of the upper layer portion is lower than an oxygen composition ratio of the lower layer portion.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a foundation layer, a stacked body, and an insulating layer. The stacked body provides on the foundation layer, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a first stacked portion and a second stacked portion. The plurality of electrode layers of the second stacked portion has a plurality of terrace portions arranged in a staircase configuration by forming a level difference in a first direction. The insulating layer provides on the plurality of terrace portions, the insulating layer includes silicon oxide as a major component. The insulating layer includes an upper layer portion and a lower layer portion. An oxygen composition ratio of the upper layer portion is lower than an oxygen composition ratio of the lower layer portion.