Semiconductor Device Staircase Electrode Thickness
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Solution Overview
Problem
In three-dimensional semiconductor memory devices, the existing staircase configuration of electrode layers faces challenges in maintaining adequate breakdown voltage due to the thinness of terrace portions, which can lead to unreliable contact hole formation and potential shorts between electrode layers.
Innovation Solution
The semiconductor device incorporates thicker terrace portions in a staircase configuration by increasing the film thickness of these portions, which prevents contact holes from extending through and reduces the distance between terrace portions and adjacent electrode layers, thereby enhancing breakdown voltage by causing specific edges of electrode layers to recede and tilt, widening the distance and improving electrical insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the film thickness of terrace portions is increased, then the breakdown voltage between electrode layers is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies local quality by making the terrace portions of electrode layers locally thicker than other portions. Specifically, the first electrode layer has a first terrace portion with a first thickness that is greater than the thickness of other portions, and the second electrode layer has a second terrace portion with a second thickness greater than other portions. This localized thickness increase enhances the breakdown voltage at critical interfaces without requiring the entire device structure to be more complex.
Solution Approach 2:
The patent resolves the contradiction by transitioning from a uniform two-dimensional electrode layer structure to a three-dimensional staircase configuration with varying thicknesses. The electrode layers are stacked in a staircase manner where terrace portions protrude in the planar direction, creating multiple levels. This dimensional change allows the terrace portions to be positioned at different heights and locations, enabling local thickness enhancement at specific interfaces while maintaining overall structural integrity.
2Ease of manufacture
If the terrace portions are made thinner to reduce device complexity, then the manufacturing process is simplified, but contact hole formation becomes unreliable and shorts may occur between electrode layers
Solution Approach 1:
The patent addresses this contradiction by implementing local quality enhancement at the terrace portions. The first electrode layer's first terrace portion and the second electrode layer's second terrace portion are made with increased thickness specifically at the locations where contact holes need to be formed. This localized thickness increase ensures reliable contact hole formation and adequate insulation between electrode layers without requiring the entire electrode structure to be uniformly thicker, thus maintaining ease of manufacture while preventing shorts.
Solution Approach 2:
The patent applies preliminary action by pre-forming the thicker terrace portions in the electrode layers before subsequent processing steps. The staircase configuration with enhanced thickness at terrace portions is established in advance, which facilitates reliable contact hole formation in later manufacturing steps. This preliminary structural preparation prevents potential shorts between electrode layers before they can occur during subsequent processing.
3Productivity
If the electrode layers are stacked closer together to increase density, then the device integration is improved, but the breakdown voltage between adjacent layers decreases
Solution Approach 1:
The patent resolves this contradiction by applying local quality enhancement at the interfaces between adjacent electrode layers. The terrace portions of the first and second electrode layers are made thicker specifically at the locations where they interface with adjacent layers. This localized thickness increase maintains adequate breakdown voltage and electrical insulation at critical interfaces even when electrode layers are stacked closely together, enabling high device integration density without compromising reliability.
Solution Approach 2:
The patent uses dimensional change by stacking electrode layers in a three-dimensional staircase configuration rather than a simple planar arrangement. The terrace portions protrude in the planar direction and are positioned at different heights, creating vertical separation between adjacent electrode layers. This three-dimensional stacking allows for higher integration density while the localized thickness enhancement at terrace portions ensures adequate breakdown voltage is maintained at each interface.
Data Source
AI summary
According to one embodiment, the first electrode layer includes a first portion and a second portion thicker than the first portion. The second electrode layer includes a third portion and a fourth portion thicker than the third portion. The fourth portion is provided on a lower level side of the second portion. The fourth portion has a level difference in a staircase configuration between the fourth portion and the second portion. The fourth portion protrudes along a first direction further than an edge of the second portion. The third electrode layer is provided between the first electrode layer and the third portion. The third electrode layer has an edge receding further than the edge of the second portion of the first electrode layer. The receding is in a reverse direction of a protruding direction of the fourth portion of the second electrode layer.