Staircase Structures for 3D Memory Double-Sided Routing
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Solution Overview
Problem
Conventional 3D memory devices face challenges in increasing storage capacity due to constrained interconnect routing and high interconnect density, which limits the flexibility of word line fan-out and narrows the process window, necessitating innovative solutions for enhanced routing and reduced density.
Innovation Solution
The implementation of staircase structures for double-sided routing in 3D memory devices, allowing interconnect routing towards both sides of the substrate, thereby increasing routing flexibility and reducing interconnect density, and potentially eliminating high-aspect-ratio interconnect structures like through-array contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional single-sided interconnect routing is used in 3D memory devices, then the routing path is simple and easy to manufacture, but the routing flexibility is constrained and interconnect density becomes high
Solution Approach 1:
The patent transitions from single-sided routing to double-sided routing by utilizing both top and bottom surfaces of the substrate for interconnect access. This dimensional expansion allows word lines to be routed out from both sides of the substrate, effectively doubling the available routing paths and reducing interconnect density on each side while maintaining routing flexibility.
2Reliability
If high-aspect-ratio interconnect structures like through-array contacts are used, then vertical connectivity is achieved, but the process window narrows and manufacturing difficulty increases
Solution Approach 1:
The patent segments the interconnect routing into two separate surfaces - top surface routing and bottom surface routing. Instead of using single high-aspect-ratio through-array contacts to achieve vertical connectivity, the design routes interconnects horizontally on both top and bottom surfaces, eliminating the need for deep vertical vias and thereby expanding the process window while maintaining connectivity.
3Productivity
If planar memory cell scaling continues, then manufacturing techniques become simpler, but memory density approaches an upper limit
Solution Approach 1:
The patent employs three-dimensional stacking architecture where memory cells are arranged vertically in multiple layers stacked on top of each other. This vertical dimensionality change allows continued increase in memory density without further lateral scaling, avoiding the fabrication complexity associated with extreme planar scaling while achieving higher capacity through the third dimension.
Data Source
AI summary
Embodiments of staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed above the substrate and including conductor/dielectric layer pairs stacked alternatingly, and an array of memory strings each extending vertically through an inner region of the memory stack. An outer region of the memory stack includes a first staircase structure disposed on the substrate and a second staircase structure disposed above the first staircase structure. First edges of the conductor/dielectric layer pairs in the first staircase structure along a vertical direction away from the substrate are staggered laterally away from the array of memory strings. Second edges of the conductor/dielectric layer pairs in the second staircase structure along the vertical direction away from the substrate are staggered laterally toward the array of memory strings.