Standalone Flash Memory Decoupling for SoC Yield and Latency
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Solution Overview
Problem
Current System-on-Chip (SoC) devices face challenges in integrating non-volatile flash memory, particularly in automotive applications, where high reliability, low latency, and high throughput are required, and the management of embedded memories becomes complex as lithography nodes approach 28 nm, leading to issues with yield, cost, power consumption, and performance.
Innovation Solution
A standalone non-volatile memory component is developed, structurally independent but associated with the SoC, using a dedicated flash memory technology, with improved access time, and a modified JTAG interface for testing, allowing for a Direct Memory Access configuration and enhanced logic circuitry to support larger memory capacities and optimize functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If embedded flash memory is integrated in SoC devices, then system integration and area efficiency are improved, but manufacturing complexity and yield management become difficult at lithography nodes below 28 nm
Solution Approach 1:
The patent separates the memory component from the logic component, creating two independent packages that communicate via standardized interfaces. This segmentation allows each component to be manufactured independently at optimal process nodes, avoiding the manufacturing complexity issues of integrating flash memory at advanced lithography nodes below 28 nm.
2Quantity of substance
If embedded flash memory capacity is increased in SoC devices, then storage capacity is improved, but access time increases and throughput decreases
Solution Approach 1:
The patent extracts the flash memory component from the logic component, creating a standalone memory package. This allows the memory to be optimized for capacity while the logic component remains optimized for fast access operations. The separation enables parallel processing where the logic unit can prepare access requests while memory operations execute independently, reducing effective access time despite large capacity.
3Productivity
If more communication channels are added to support larger memory capacities, then memory throughput is improved, but device complexity and area increase
Solution Approach 1:
The patent employs a universal standardized interface (such as PCIe or CXL) between the memory component and logic component. This single multi-functional interface can dynamically handle variable data widths and transfer rates, providing high throughput for large memory capacities without requiring multiple dedicated communication channels. The interface adapts to different memory sizes and performance requirements through software configuration rather than hardware multiplication.
Data Source
AI summary
An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.