Standard Cell Current Path Layout for Electromigration and Capacitance
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Solution Overview
Problem
As integrated circuit design progresses to smaller scales, the effects of electromigration and parasitic capacitance impose competing constraints on the width of conduction elements, making it challenging to balance reliability, durability, and size reduction in standard cells.
Innovation Solution
A method is introduced to adapt the layout of standard cells by identifying current collection paths, determining maximum current locations, and selectively sizing the width of these paths to meet minimum path width requirements, while reducing parasitic capacitance and area usage through iterative reductions and potential subdivision of conduction paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of the current collection path is increased to satisfy electromigration constraints, then the reliability is improved, but the area of the standard cell increases and parasitic capacitance increases
Solution Approach 1:
The current collection path is designed with non-uniform width along its length. The width is selectively increased at locations where maximum current flow occurs to satisfy electromigration constraints, while the width is reduced at other locations to minimize area and parasitic capacitance. This local variation in quality (width) allows the path to satisfy reliability requirements at critical points without unnecessarily increasing overall area.
Solution Approach 2:
The current collection path is divided into multiple segments with different width requirements. By identifying current collection points and determining maximum current locations, the path is segmented into regions that can be independently optimized - with wider sections at high-current locations and narrower sections at low-current locations, thereby resolving the contradiction between reliability and area.
2Reliability
If the width of the current collection path is increased to satisfy electromigration constraints, then the reliability is improved, but the parasitic capacitance increases
Solution Approach 1:
The width of the current collection path is locally increased only at specific locations where maximum current flow occurs, rather than uniformly across the entire path. This localized widening satisfies electromigration constraints at critical points while minimizing the overall parasitic capacitance that would result from uniformly increasing the width throughout the path.
Solution Approach 2:
The current collection path is segmented into regions with different current densities and electromigration requirements. By analyzing current contributions from multiple current collection points, the path is divided into segments that can be independently sized, allowing parasitic capacitance to be minimized while maintaining reliability at high-current segments.
3Area of stationary object
If the width of the current collection path is reduced to minimize area, then the area is reduced, but the electromigration constraints are violated
Solution Approach 1:
The current collection path employs variable width design where the width is reduced to minimum acceptable values at locations where current flow is low, thereby minimizing area. However, at locations where maximum current flow occurs, the width is locally increased to satisfy electromigration constraints, ensuring reliability is not compromised despite overall area reduction.
Solution Approach 2:
The width of the current collection path is dynamically adjusted along its length based on the current flow characteristics at different locations. By analyzing the contribution of multiple current collection points to the total current at each location, the path width is optimized dynamically - narrow where current is low, wide where current is maximum - resolving the contradiction between area and reliability.
Data Source
AI summary
A method of adapting a layout of a standard cell of an integrated circuit is provided. A current collection path in the standard cell is selected which connects components within the standard cell to an output connection, wherein the current collection path is arranged to collect current from the components at a plurality of current collection points arranged along its length. A maximum current location on the current collection path is determined at which a maximum possible current flow in the current collection path will occur if the output connection is connected there, the maximum possible current flow being a sum of current contributions from the current collection points. A maximum width of the current collection path at the maximum current location is determined such that the maximum width satisfies a minimum path width requirement with respect to the maximum possible current flow. Then a local width of the current collection path at a selected distance from the maximum current location is determined, the local width being less than or equal to the maximum width, such that the local width satisfies the minimum path width requirement with respect to a maximum local current that will occur at the selected distance, the maximum local current being a sum of the current contributions from those current collection points which contribute to the local current.