Standard Cell Pin Layout Using Perpendicular Layers to Ease Routing
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Solution Overview
Problem
Existing integrated circuits face challenges in minimizing routing congestion and optimizing area as they strive for high performance, high speed, and multifunctionality, leading to inefficiencies in layout structures.
Innovation Solution
The integrated circuit design incorporates a first layer extending in a first direction and a second layer perpendicular to it, with electrical connections to standard cells, including a gate line and contact layer, to optimize routing and reduce congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of the integrated circuit is increased to achieve high performance and high speed, then the functionality and processing speed are improved, but routing congestion increases and layout optimization becomes more difficult
Solution Approach 1:
The patent applies dimensionality change by utilizing multiple metal layers (first layer and second layer) stacked vertically to route signals. The first layer extends in a first direction and the second layer extends in a second direction perpendicular to the first direction, allowing signals to be routed in three-dimensional space rather than confined to a single plane. This vertical stacking enables high integration while maintaining routing efficiency by distributing interconnects across multiple layers, thereby reducing congestion in any single layer.
2Device complexity
If more layers are added to reduce routing congestion, then routing efficiency is improved, but the area and complexity of the integrated circuit increase
Solution Approach 1:
The patent segments the routing function across multiple metal layers, with each layer dedicated to specific routing directions. The first layer is configured to extend in a first direction and the second layer extends in a second direction perpendicular to the first direction. This segmentation allows signals to be routed efficiently in different directions on different layers, reducing the need for excessive vias and reducing overall routing complexity while maintaining a compact area.
3Area of stationary object
If standard cells are densely packed to optimize area, then the area of the integrated circuit is reduced, but turnaround time increases due to routing difficulties
Solution Approach 1:
The patent utilizes vertical layering to resolve the conflict between dense cell packing and routing efficiency. By extending the first layer in a first direction and the second layer in a perpendicular second direction, signals can be routed between densely packed standard cells without requiring long horizontal traces. This three-dimensional routing approach enables compact cell placement while maintaining short signal paths, thereby reducing turnaround time despite high density.
Data Source
AI summary
An example integrated circuit includes a first layer that extends in a first direction and a second layer that is disposed below the first layer. The second layer extends in a second direction perpendicular to the first direction, is electrically connected to the first layer, and corresponds to a first signal pin of a first standard cell among a plurality of standard cells. A position of the first layer in the second direction is substantially the same as a position of a first cell boundary, among a plurality of cell boundaries of the plurality of standard cells in the first direction, in the second direction.