Standard Cell Layouts with Virtual Grid Alignment
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Solution Overview
Problem
The existing methods for designing integrated circuits face challenges in efficiently routing metal lines to align with input/output ports of standard cells, often requiring additional layers of metal lines and increasing the complexity of interconnection routing, which can lead to resource constraints and suboptimal performance.
Innovation Solution
The approach involves using a predetermined nominal minimum pitch for virtual grid lines and standard cells, allowing for the alignment of input/output ports with metal lines, and employing a placing and routing software tool to arrange metal lines along these grid lines, thereby reducing the need for additional routing resources and enhancing interconnection performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard cell layouts are used with predetermined functions, then the design process is simplified and standardization is improved, but the alignment of input/output ports with metal lines becomes difficult requiring additional routing layers
Solution Approach 1:
The patent applies preliminary action by pre-defining the positions of input/output ports in standard cell layouts to coincide with virtual grid lines before the routing process begins. This advance positioning ensures that metal lines can be directly routed along the grid lines without requiring additional routing layers, thus simplifying the overall routing complexity while maintaining standardization benefits
Solution Approach 2:
The patent introduces virtual grid lines as an intermediary element that mediates between the standard cell layouts and the metal line routing. These grid lines serve as a reference framework that guides the placement of input/output ports and the routing of metal lines, enabling automatic alignment and reducing the need for additional routing layers
2Manufacturing precision
If additional layers of metal lines are used to align with input/output ports, then the alignment is achieved, but the number of metal layers increases consuming more resources
Solution Approach 1:
The patent applies preliminary action by pre-positioning input/output ports at locations that coincide with virtual grid lines before the routing process. This advance planning ensures that metal lines can be routed directly along the grid lines to reach the ports, achieving precise alignment without requiring additional metal layers, thus reducing the quantity of metal layers used
Solution Approach 2:
The patent makes the virtual grid lines serve multiple functions: they act as alignment references for input/output port placement, as routing guides for metal lines, and as a coordinate system for the entire layout. This multi-functionality enables a single set of grid lines to achieve both precise alignment and efficient routing without requiring additional layers
3Adaptability or versatility
If the cell height is a non-integral multiple of the nominal minimum pitch, then more flexible layout arrangements are possible, but the alignment with metal lines becomes more difficult
Solution Approach 1:
The patent resolves the contradiction by introducing a new dimension - the vertical dimension perpendicular to the metal line routing direction. By allowing cell heights to be non-integral multiples of the nominal minimum pitch in this perpendicular dimension, the patent enables layout flexibility without affecting the alignment precision in the routing dimension, as the virtual grid lines provide the necessary alignment reference independent of cell height
Data Source
AI summary
An integrated circuit designing system includes a non-transitory storage medium encoded with a first set of standard cell layouts and a second set of standard cell layouts both being configured to perform a predetermined function. The predetermined manufacturing process having a nominal minimum pitch (T) of metal lines. Each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) wherein the cell height is a non-integral multiple of the nominal minimum pitch. A hardware processor communicatively is coupled with the non-transitory storage medium and is configured to execute a set of instructions for generating an integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts and the nominal minimum pitch; and creating a data file corresponding to the integrated circuit layout.