Standby PLL Clock Control for Low-Power Radio Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing UWB systems face high energy consumption during standby RF states due to the continuous operation of phase-locked loops (PLL) for maintaining timing accuracy, which contradicts the reduced energy consumption requirements.
Innovation Solution
A PLL architecture with adjustable power control and high temporal resolution is implemented, using a synchronization circuit and auxiliary counter to manage PLL activation and deactivation, reducing energy consumption during standby states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the PLL is kept constantly operating to maintain timing accuracy during standby RF state, then timing precision is improved, but energy consumption increases
Solution Approach 1:
The patent implements periodic action by enabling the PLL only during specific intervals when timing updates are required, rather than keeping it continuously operating. The MAC_TIMER periodically triggers PLL activation to synchronize the clock signal, allowing the system to maintain timing precision while consuming less energy during standby periods when high-precision timing is not critical.
Solution Approach 2:
The patent applies dynamics by making the PLL operational state adjustable and adaptive. The system dynamically switches between PLL enabled and disabled states based on operational requirements. The clock generator is configured to provide different clock frequencies depending on whether the PLL is active, allowing the system to adapt its timing precision and energy consumption characteristics to current needs.
2Use of energy by moving object
If the clock speed is reduced to lower PLL power consumption, then energy consumption is improved, but timing resolution deteriorates
Solution Approach 1:
The patent implements dynamic clock frequency adjustment where the clock generator provides different clock frequencies based on operational mode. During active transmission/reception, a higher clock frequency is provided for precise timing. During standby mode, the clock frequency is reduced or the PLL is disabled, lowering power consumption while maintaining sufficient timing resolution through periodic synchronization.
Solution Approach 2:
The patent changes the clock frequency parameter dynamically based on operational state. The clock generator is configured to output different frequencies, and the system selects appropriate frequency levels to balance timing resolution requirements with power consumption constraints. This parameter adjustment allows the system to achieve low power consumption during standby while maintaining adequate timing precision when needed.
Data Source
AI summary
Method of operating a radio communication system during a stand-by time interval in a stand-by state. The method comprises: applying clock division processing to a reference clock signal and producing a divided clock signal; applying PLL processing to the divided clock signal producing a PLL clock signal; receiving at least one input signal; when the input signal has a first logic value, interrupting applying PLL processing to the divided clock signal and enabling counting clock signal edges of the divided clock signal; when said counting clock signal edges reaches a first target count value, restarting applying PLL processing; continuing counting clock signal edges until reaching a second target count value; when said counting reaches the second target count value, issuing and sampling an end-count signal based on the PLL clock signal, producing a timing clock signal as a result and providing the timing clock signal to a user circuit.