Star-Configured DCO Layout for Stable Chirp Linearity
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Solution Overview
Problem
Existing Digitally Controlled Oscillators (DCOs) in Phase-Locked Loops (PLLs) suffer from parasitic inductance issues that invalidate calibration due to lock-state dependency between compensation and modulation capacitor banks, leading to degraded chirp linearity and frequency errors.
Innovation Solution
The DCO is arranged in a star configuration where modulation and compensation capacitor banks are connected via separate paths to a negative transconductance stage, reducing parasitic inductance and mitigating lock-state dependency, thereby maintaining calibration integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If compensation and modulation capacitor banks are connected via shared paths in conventional DCOs, then device complexity is reduced, but parasitic inductance increases causing calibration invalidation and frequency errors
Solution Approach 1:
The patent segments the capacitor bank connections by providing separate first and second paths for compensation capacitor banks and modulation capacitor banks, respectively. This physical separation eliminates the shared path that causes parasitic inductance, allowing each capacitor bank to be controlled independently without mutual interference while maintaining manageable device complexity.
2Ease of manufacture
If compensation and modulation capacitor banks share common paths, then manufacturing is simplified, but lock-state dependency invalidates calibration leading to degraded chirp linearity
Solution Approach 1:
The patent implements separate first and second paths for compensation and modulation capacitor banks, physically segmenting the signal paths to eliminate lock-state dependency. This segmentation ensures that calibration performed on modulation capacitor banks remains valid regardless of compensation capacitor bank states, thereby maintaining high chirp linearity without complicating the manufacturing process.
3Measurement precision
If separate paths are used for compensation and modulation capacitor banks, then parasitic inductance is reduced and calibration integrity is maintained, but device complexity increases
Solution Approach 1:
The patent segments the DCO into distinct first and second paths with dedicated capacitor banks for compensation and modulation functions. This segmentation achieves frequency accuracy by eliminating parasitic inductance and lock-state dependency, while the modular structure keeps the increased complexity manageable through clear functional separation.
Solution Approach 2:
The patent applies local quality by optimizing specific paths for specific functions: the first path is dedicated to compensation capacitor banks for frequency stabilization, while the second path is dedicated to modulation capacitor banks for chirp generation. This localized optimization ensures each path performs its function with high precision without being affected by the other path's operations.
4Volume of moving object
If capacitor banks are connected via shared paths, then the DCO structure is more compact, but parasitic inductance causes calibration to be invalidated by lock-state changes
Solution Approach 1:
The patent segments the capacitor bank connections into separate first and second paths, physically isolating compensation and modulation functions. This segmentation maintains calibration validity by preventing lock-state changes in compensation capacitor banks from affecting modulation capacitor bank calibration, while the compact layout of separate paths minimizes the increase in physical size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement enhances chirp linearity and robustness by minimizing the impact of parasitic inductance on modulation capacitor banks, ensuring stable frequency modulation and improved accuracy.
Implementation Method 1
a negative transconductance stage coupled to a first node, a second node, and a reference node
Implementation Method 2
a first plurality of capacitor banks coupled to a first path and a second path... a second plurality of capacitor banks coupled to a third path and a fourth path... including at least one modulation capacitor bank
Data Source
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AI summary
The present disclosure relates to an oscillator, such as a Digitally Controlled Oscillator (DCO), having first capacitor banks coupled to a first path and a second path, the first path connecting a first node to a first output node, and the second path connecting a second node to a second output node, and second capacitor banks coupled to a third path and a fourth path, the third path being connected to the first node, the fourth path being connected to the second node, the first and second paths being separate from the third and fourth paths, and the second capacitor banks including at least one modulation capacitor bank