State Managed Asynchronous Runtime for Image Processing Pipelines
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Solution Overview
Problem
Existing computer processors are limited in their ability to efficiently process varied and time-critical image processing cycles due to fixed pipeline stages and resource bottlenecks, which restricts their flexibility and performance in heavy-duty industrial machine vision applications.
Innovation Solution
A state-managed asynchronous pipelined architecture is implemented, allowing multiple image processing cycles to be executed independently in parallel pipelines, each with pre-existing cycle data containers, to fully utilize hardware resources and scale performance with the number of processor cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a fixed pipeline stage configuration is used in computer processors, then the system structure is simple and stable, but the processing flexibility and adaptability to varied image processing cycles deteriorates
Solution Approach 1:
The patent implements dynamic pipeline configuration where the number of pipeline stages and their functionality can be adjusted at runtime based on the specific image processing cycle requirements. Each pipeline stage is dynamically created or activated depending on the trigger event and processing needs, allowing the system to adapt between simple and complex processing configurations without sacrificing structural stability.
Solution Approach 2:
The processing system is divided into independent, modular pipeline stages that can be individually configured and executed. Each stage represents a discrete functional unit that can be independently managed, allowing flexible combination and recombination of processing steps across multiple parallel pipelines to handle varied image processing cycles.
2Device complexity
If multiple image processing cycles are processed sequentially in a single pipeline, then the system complexity is low, but the processing speed and productivity deteriorates
Solution Approach 1:
The patent transitions from single-dimensional sequential processing to multi-dimensional parallel processing by creating multiple independent pipelines that execute simultaneously. Each pipeline operates as an independent processing dimension, allowing multiple image processing cycles to progress concurrently through different stages, thereby exponentially increasing throughput without proportionally increasing system complexity.
Solution Approach 2:
Pipeline stages are pre-configured and staged ready before actual processing begins. The system prepares multiple pipelines with pre-allocated resources and pre-defined stage configurations, enabling immediate parallel execution when trigger events occur, thus reducing initialization overhead and maximizing processing speed.
3Device complexity
If hardware resources are allocated to a single image processing cycle, then the resource allocation is simple, but the resource utilization efficiency deteriorates
Solution Approach 1:
Hardware resources are designed with multi-functionality, where the same physical resources (processors, memory, I/O interfaces) can be dynamically allocated to different image processing cycles across multiple pipelines. Each resource can serve multiple processing contexts sequentially or concurrently, maximizing utilization efficiency without requiring dedicated resources for each cycle.
Solution Approach 2:
The system maintains continuous utilization of hardware resources by keeping multiple pipelines actively processing different image cycles simultaneously. Resources transition smoothly between different processing tasks without idle gaps, ensuring that computational units, memory bandwidth, and I/O channels are consistently engaged in useful work across the parallel pipeline ensemble.
4Device complexity
If a synchronous processing architecture is used, then the control logic is simple, but the processing time and bottleneck delays worsen
Solution Approach 1:
The patent implements asynchronous processing where each pipeline stage and pipeline itself can progress at its own optimal speed without being constrained by synchronous clock cycles. Trigger events initiate processing independently, and each stage advances when its data is ready, eliminating wait states and bottleneck delays inherent in synchronous architectures while managing control logic through event-driven mechanisms.
Data Source
AI summary
This application is directed to image processing. An electronic device identifies a plurality of image processing cycles associated with a temporal sequence of triggers, and each image processing cycle is created in response to one or more respective trigger events. The plurality of image processing cycles is to a plurality of parallel pipelines. For each parallel pipeline, the electronic device pulls a respective cycle data container from a cycle data pool. A first image processing cycle is processed in a first parallel pipeline to generate first report data, independently of processing remaining image processing cycles in respective remaining parallel pipelines. The first report data is reported to a client device coupled to the electronic device for further processing (e.g., storage, classification, analysis, and/or visualization).