State Retention Verification via Behavioral Assertions
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Solution Overview
Problem
The complexity of formal verification in integrated circuit designs increases exponentially with the number of state bits, particularly due to the need for state retention elements in power management, which complicates the modeling of power shutoff effects without adding additional state bits.
Innovation Solution
An abstract state retention circuit model is introduced, using synchronous D Flip Flops and multiplexers to manage power control signals, allowing for efficient modeling of state retention without increasing the design's state space, thereby reducing the complexity of formal verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional state retention bits are added to retain state during power shutdown, then state retention capability is improved, but formal verification complexity increases exponentially
Solution Approach 1:
The patent extracts the state retention functionality from the physical circuit level and models it at the behavioral level using assertions. Instead of adding physical state bits to the circuit, the invention creates a separate verification model that captures the expected state retention behavior through assertions, thereby avoiding the exponential complexity increase in formal verification while maintaining state retention capability
Solution Approach 2:
The patent creates a behavioral copy of the state retention behavior through assertions rather than copying the actual state bits. The assertions capture the expected behavior of state elements during power shutdown and recovery, allowing verification of state retention without duplicating the state space in the verification model
2Reliability
If additional state bits are created for each state element to save system state, then state retention is achieved, but the number of state bits in verification model increases
Solution Approach 1:
The invention extracts the essential state retention behavior from the detailed circuit implementation and represents it through high-level assertions. This behavioral modeling approach captures state retention requirements without requiring additional state bits in the verification model, thereby reducing the quantity of state elements while maintaining retention functionality
Solution Approach 2:
The patent changes the representation parameter of state retention from physical state bits to behavioral assertions. By transforming the problem from a bit-level representation to a behavior-level representation, the invention reduces the number of state bits in the verification model while preserving the state retention functionality through assertion-based verification
Data Source
AI summary
Verification model of static state retention behavior of a state saving element design during power shut off of the state saving element in an integrated circuit design including: creating in a computer readable medium a model of a single edge triggered state saving element; and creating in the computer readable medium clock gate logic that suspends saving of new states by the single state saving element upon the occurrence of a first state retention signal in preparation for power shut off.