Stateful Vector Permutation With Shared Buffers for Large Vectors

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing vector permutation operations in processors, particularly large vector permutations, face inefficiencies due to quadratic complexity in micro-ops, leading to resource monopolization in the processor pipeline, and require excessive storage capacity for intermediary results.

Innovation Solution

Implementing a stateful vector group permutation mechanism that reduces storage requirements by sharing register capacity between intermediary results and expanded indexes, utilizing an index expander to convert element indexes into byte indexes, and optimizing execution sequencing to minimize unnecessary operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional vector permutation operations are used, then the operation can be completed, but the processor pipeline resources are monopolized due to quadratic complexity in micro-ops

Engineering Contradiction:
Improveexecution speedVSAvoidmicro-ops complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the vector permutation operation into distinct phases: gathering elements from source vector registers using index values, storing intermediary results in a buffer, and then permuting elements to destination registers. This segmentation allows each phase to be optimized independently and prevents quadratic complexity by avoiding redundant micro-ops across the entire operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by expanding index values to byte offsets before the actual permutation operation, and by pre-storing intermediary results in a buffer during the gather phase. This preliminary preparation eliminates the need for repeated index calculations during the permutation phase, reducing micro-ops complexity while maintaining productivity.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If traditional vector permutation operations are used, then the operation can be completed, but excessive storage capacity is required for intermediary results

Engineering Contradiction:
Improveprocessing capabilityVSAvoidstorage capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent merges the storage of intermediary results with the storage of expanded index byte offsets by using the same buffer for both purposes. During the gather phase, the buffer stores intermediary results; during the permutation phase, the same buffer stores expanded byte offsets. This merging eliminates the need for separate storage structures, reducing total storage capacity requirements while maintaining full processing capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs a buffer that is reused across different phases of the operation. After the gather phase completes and intermediary results are no longer needed, the buffer is recovered and reused for storing expanded byte offsets during the permutation phase. This discarding and recovering approach maximizes storage utilization and minimizes the total storage capacity required.

Inventive Principle:
Principle #34Discarding and recovering

3Productivity

If traditional vector permutation operations are used, then the operation can be completed, but integrated circuit area increases due to excessive storage requirements

Engineering Contradiction:
Improvevector permutation capabilityVSAvoidintegrated circuit area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent implements a universal buffer structure that serves multiple functions: storing intermediary results during the gather phase, storing expanded byte offsets during the permutation phase, and potentially serving as a general-purpose register file. This multi-functionality eliminates the need for dedicated storage structures for each data type, reducing integrated circuit area while maintaining full vector permutation capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs dynamic buffer allocation where the same physical storage resources are dynamically assigned to different data structures based on the current phase of execution. During gathering, the buffer dynamically stores intermediary results; during permutation, it dynamically stores expanded byte offsets. This dynamic utilization reduces the total storage capacity needed, thereby reducing integrated circuit area.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12423099B2Stateful vector group permutation with storage reuse
Publication Date: 2025.09.23 SIFIVE INC
  • US12423099B2 patent drawing
  • US12423099B2 patent drawing
  • US12423099B2 patent drawing

AI summary

Systems and methods are disclosed for stateful vector group permutation with storage reuse. For example, some methods may include expanding an element index from a vector of indices to obtain byte indices for respective bytes of a corresponding element; storing the byte indices in corresponding bytes of an intermediate result operand buffer; updating bits in a completion flags buffer to indicate that the corresponding bytes of the intermediate result operand buffer store indices; identifying bytes of an element of the vector of source data pointed to by the element index based on the byte indices stored in the intermediate result operand buffer; overwriting the byte indices in the intermediate result operand buffer with the identified bytes; and, responsive to overwriting the byte indices, updating the corresponding bits in the completion flags buffer to indicate that the corresponding bytes store data to be written to the destination vector.