Static Dataflow Processor for Parallel N-D Affine Transforms
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Solution Overview
Problem
Conventional CPUs and GPUs incur significant overhead due to dynamic reconfiguration and implicit instruction dependencies when performing affine transformations on images, which affects the efficiency and feasibility of training neural networks and other applications requiring large numbers of such transformations.
Innovation Solution
A statically reconfigurable dataflow architecture processor (SRDAP) performs N-dimensional affine transformations by statically configuring its datapath and scratchpad memories using a dataflow program, eliminating the need for dynamic instruction fetching and handling of implicit dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional CPUs and GPUs are used to perform affine transformations, then the transformations can be performed with flexible programming, but significant overhead is incurred due to dynamic reconfiguration and implicit instruction dependencies
Solution Approach 1:
The patent applies dynamics by making the processor statically reconfigurable rather than dynamically reconfigurable. The datapath architecture is configured once for a specific affine transformation type (rotation, scaling, shearing, etc.) and then operates efficiently without the overhead of dynamic instruction fetching and dependency resolution that plagues conventional CPUs and GPUs.
Solution Approach 2:
The patent segments the affine transformation computation into distinct functional units within the datapath, including coordinate transformation units, matrix multiplication units, and pixel value interpolation units. This segmentation allows each unit to be optimized for its specific function and operate in parallel, eliminating the sequential overhead of conventional processors.
2Adaptability or versatility
If affine transformations are performed using conventional processors, then various transformation types can be supported, but the time required for each transformation increases due to overhead
Solution Approach 1:
The patent supports multiple transformation types (rotation, scaling, shearing, reflection) by changing the parameters of the affine transformation matrix rather than changing the processor architecture dynamically. The statically configured datapath can efficiently execute different transformation types by loading different matrix parameters, maintaining versatility without the time overhead of dynamic reconfiguration.
3Ease of operation
If dynamic reconfiguration is used in conventional processors, then program flexibility is maintained, but overhead from instruction fetching and dependency handling reduces efficiency
Solution Approach 1:
The patent applies preliminary action by pre-configuring the datapath architecture for a specific affine transformation type before execution. The processor is statically configured with the appropriate transformation matrix and computational pipeline, eliminating the need for runtime instruction fetching and dependency resolution. This preliminary configuration enables efficient parallel execution without the overhead of dynamic reconfiguration.
Data Source
AI summary
A statically reconfigurable dataflow architecture processor (SRDAP) performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image includes L address pattern memory units (PMUs) comprising a memory arranged as a vector of L banks, and L corresponding data PMUs. Each data PMU receives a copy of the input image. In parallel: each address PMU writes an L-vector of addresses of input pixels to the vector of L banks and reads a single address of the written L-vector of addresses from a predetermined bank corresponding to a PMU number of the address PMU among the L address PMUs, and each data PMU receives the single address from the corresponding address PMU and uses it to read a single input pixel from the data PMU memory. A tree of pattern compute units coalesces the L single input pixels into an L-vector of input pixels.