Static RAM Hierarchical Bit Line Segmentation for Power Reduction
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Solution Overview
Problem
Reducing power consumption in static RAM (SRAM) while maintaining operation speed is challenging due to variations in transistor characteristics, which affect the read rate and increase power consumption when trying to lower the operating voltage.
Innovation Solution
A hierarchical structure is implemented with global and local bit line pairs, where the local bit line pairs are connected to global bit line pairs via switches, allowing for efficient voltage amplification and reduced power consumption by minimizing the capacitance of the global bit line pairs, thereby stabilizing the read operation across varying transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the operating voltage is reduced to lower power consumption, then power consumption is reduced, but the read rate decreases due to variations in transistor characteristics
Solution Approach 1:
The bit line is divided into multiple segments: a first bit line connected to memory cells and a second bit line connected to the sense amplifier. This segmentation allows the first bit line to have smaller capacitance for faster charging/discharging (improving read rate) while the second bit line can be optimized for sensing, thereby resolving the contradiction between speed and power consumption at reduced voltages.
2Use of energy by moving object
If the operating voltage is reduced to lower power consumption, then power consumption is reduced, but erroneous reads occur due to transistor characteristics variations
Solution Approach 1:
A buffer circuit is introduced as an intermediary between the first bit line and the sense amplifier. The buffer circuit includes a first capacitor connected between the first bit line and a first node, and a second capacitor connected between the first node and the second bit line. This intermediary structure isolates the sense amplifier from direct connection to the memory cells, providing signal conditioning that prevents erroneous reads caused by transistor variations while maintaining low power consumption at reduced voltages.
3Productivity
If a long bit line is used to connect multiple memory cells, then more memory cells can be accessed, but charge/discharge time increases reducing operation speed
Solution Approach 1:
The bit line is segmented into a first bit line connecting memory cells and a second bit line connecting to the sense amplifier. The first bit line can be shorter and have smaller capacitance for faster operation, while the second bit line extends to the sense amplifier. This segmentation allows the system to access more memory cells without the entire bit line being long, thereby maintaining high operation speed.
Solution Approach 2:
The buffer circuit with capacitors acts as an intermediary that decouples the first bit line from the sense amplifier. This allows the first bit line to be optimized for speed with smaller capacitance, while still enabling connection to multiple memory cells through the buffer circuit, thus resolving the contradiction between access capacity and operation speed.
Data Source
AI summary
A static RAM includes a plurality of word lines, a plurality of global bit line pairs, a plurality of static-type memory cells, a plurality of sense amplifiers, a plurality of local bit line pairs provided in correspondence with each global bit line pair, and a plurality of global switches, wherein the plurality of static-type memory cells is connected to the corresponding local bit line pair in response to a row selection signal, and at the time of read, the row selection signal is applied to the word line and after the corresponding local bit line pair is brought into a state corresponding to contents stored in the memory cell, application of the row selection signal is stopped and then the corresponding global switch is brought into a connection state and after changing the state of the global bit line pair, the corresponding sense amplifier is operated.