Static Timing Analysis for Fake Fault Elimination
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Solution Overview
Problem
Conventional static timing analysis in integrated circuit design is inefficient due to manual adjustment of cell delays and propagation delays, leading to time-consuming operations and prolonged design cycles, as it requires repeated iterations to eliminate fake faults.
Innovation Solution
A new static timing analysis method that automatically adjusts cell delays in integrated circuits by determining propagation delays in both worst-based and path-based modes, allowing for the elimination of fake faults prior to gate-level simulations, thereby shortening the design cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual adjustment of cell delays and propagation delays is performed to eliminate fake faults, then the timing requirement can be met, but the design cycle becomes prolonged and time-consuming
Solution Approach 1:
The patent performs preliminary determination of whether propagation delay exceeds timing requirement before manually adjusting cell delays. By using path-based mode to identify paths that truly exceed timing requirements, the method prevents unnecessary manual adjustments and iterations, thereby reducing design cycle duration while ensuring timing compliance is achieved only when necessary
Solution Approach 2:
The patent implements a feedback mechanism where the determination result from path-based mode feeds back into the manual adjustment process. When the propagation delay is determined to exceed the timing requirement, manual adjustment is triggered; when it does not exceed, adjustment is avoided. This feedback loop eliminates unnecessary iterations and shortens the design cycle while maintaining timing requirement compliance
2Reliability
If repeated iterations are performed to eliminate fake faults by manually lowering cell delays, then the circuit meets timing requirement, but the operation becomes inefficient and time-consuming
Solution Approach 1:
The patent performs preliminary determination using path-based mode to identify whether propagation delay truly exceeds timing requirement before initiating manual adjustment iterations. This preliminary check prevents unnecessary iteration cycles by accurately identifying only those cases where adjustment is needed, thereby improving design efficiency while ensuring timing compliance is achieved through targeted adjustments
Solution Approach 2:
The system performs self-determination through path-based mode analysis to identify whether timing adjustment is needed, eliminating the need for repeated trial-and-error iterations. The automatic determination mechanism serves the adjustment process by providing accurate guidance on when and where adjustments are necessary, improving productivity while maintaining reliable timing compliance
Data Source
AI summary
A method for determining the propagation delay of each path in an integrated circuit is provided herein. The method includes determining, in a worst-based mode, whether a propagation delay of a selected path exceeds a timing requirement; determining, in a path-based mode, whether the propagation delay of a selected path exceeds the timing requirement; and when the selected path exceeds the timing requirement in the path-based mode, lowering the cell delay of each cell in the selected path.