Stepped Connection Plates for 3D Memory Array Isolation
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently connecting and isolating memory array regions due to the complexity of through-memory-level metal via structures and stepped connection plates, which affects the reliability and performance of NAND string memory devices.
Innovation Solution
A three-dimensional semiconductor device is designed with a through-memory-level metal via structure and stepped connection plates, where dielectric wall structures and backside trenches are used to create a connection region for electrical connectivity between memory array regions, allowing for the formation of continuous and isolated memory stack structures and electrical connections through the use of connection metal interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-memory-level metal via structures and stepped connection plates are used to connect memory array regions, then electrical connectivity between regions is achieved, but device complexity increases
Solution Approach 1:
The connection plate is divided into multiple segments at different elevations (first connection plate portion at first elevation, second connection plate portion at second elevation). This segmentation allows the structure to connect memory array regions at different levels without requiring a single complex through-memory-level via, thereby reducing overall device complexity while maintaining electrical connectivity.
Solution Approach 2:
The connection structure transitions from a single vertical dimension (through-memory-level via) to multiple vertical dimensions (stepped connection plates at different elevations). By utilizing multiple elevation levels, the patent achieves connectivity between memory array regions while distributing the connection function across different vertical planes, reducing the complexity of any single connection point.
2Reliability
If dielectric wall structures and backside trenches are used to isolate memory array regions, then region isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The backside trenches and dielectric wall structures are formed prior to forming the connection plates and memory stack structures. This preliminary action establishes the isolation framework early in the manufacturing process, allowing subsequent steps to proceed more easily without requiring complex reconfiguration, thereby improving ease of manufacture while maintaining effective region isolation.
Solution Approach 2:
The dielectric wall structures serve as intermediary elements between the backside trenches and the memory array regions. These dielectric walls fill the trenches and provide the actual isolation function, while the trench structure itself provides the framework. This intermediary approach simplifies the manufacturing process by separating the trench formation step from the isolation material deposition step.
3Reliability
If continuous electrically conductive layers extend through connection regions, then connectivity between memory array regions is enhanced, but selectivity in patterning becomes more difficult
Solution Approach 1:
The electrically conductive layers are given different local qualities through selective patterning. The first subset of conductive layers (word lines and source select gates) continuously extends through the connection region, while the second subset (drain select gates) is physically divided into separate portions. This local differentiation allows each conductive layer type to be patterned and connected according to its specific electrical requirements, enhancing connectivity where needed while maintaining patterning selectivity through material or structural differentiation.
Data Source
AI summary
Memory stack structures and dielectric wall structures are formed through a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers. Backside trenches are formed to divide the vertically alternating sequence into multiple alternating stacks. First portions of the continuous sacrificial material layers are replaced with electrically conductive layers. A connection region including a pair of dielectric wall structures is provided between a first memory array region and a second memory array region of a first alternating stack. Second portions of the continuous sacrificial material layers remain between the pair of dielectric wall structures as a vertical stack of dielectric plates. An upper subset of the first electrically conductive layers is patterned and is divided into multiple discrete portions. The multiple discrete portions are electrically connected by a respective set of connection metal interconnect structures. A metal via structure may be formed through the dielectric plates.