Semiconductor Package Substrate With Stepped Electrodes
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Solution Overview
Problem
The reduction in size and gap between electrodes in semiconductor packages poses challenges such as limitations in substrate fabrication technology, increased electrical resistance, and signal delay due to mutual interference, which existing wire bonding technologies struggle to address effectively.
Innovation Solution
A substrate with a multi-layered structure featuring a core layer, wiring layers, and a passivation layer, where electrodes are formed in a stepped shape, allowing for enhanced wire bonding workability and reduced package size by eliminating the need for gaps between electrodes, using conductive connection members like gold wires for electrical connections between semiconductor chips and the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If electrode sizes and gaps between electrodes are reduced to make packages lighter and smaller, then package size is reduced, but electrical resistance increases and signal delay occurs due to mutual interference
Solution Approach 1:
The patent transitions from planar electrode arrangement to three-dimensional stacked electrode configuration. Multiple electrodes are arranged in vertical stacks with alternating polarity, utilizing the third dimension (height) to reduce lateral spacing. This dimensional change allows smaller package footprint while maintaining adequate electrical isolation through vertical stacking, thereby reducing mutual interference and signal delay while minimizing package size.
Solution Approach 2:
The patent implements nested electrode structures where multiple electrodes are stacked vertically within the same lateral footprint. Positive and negative electrodes are alternately stacked in a nested arrangement, allowing multiple electrical connection points to occupy the same planar space. This nesting approach reduces the overall package area while maintaining sufficient electrical isolation between adjacent electrodes through vertical separation.
2Volume of moving object
If electrode sizes and gaps between electrodes are reduced to make packages lighter and smaller, then package size is reduced, but substrate fabricating technology limits are encountered
Solution Approach 1:
The patent addresses substrate fabrication limitations by moving from two-dimensional planar processing to three-dimensional stacked architecture. This dimensional transition allows standard substrate fabrication techniques to be applied vertically through multiple layers, circumventing lateral processing limits. The vertical stacking approach maintains compatibility with existing fabrication technologies while achieving miniaturization through the third dimension.
Solution Approach 2:
The patent divides the electrode structure into discrete, alternating positive and negative electrode segments stacked vertically. This segmentation allows each electrode layer to be fabricated and processed independently using standard substrate techniques, while the overall stacked structure achieves miniaturization. The segmented approach makes the manufacturing process more manageable by breaking down complex three-dimensional patterns into repeatable two-dimensional layers.
3Volume of moving object
If electrode sizes and gaps between electrodes are reduced to make packages lighter and smaller, then package size is reduced, but mutual interference between electrodes increases
Solution Approach 1:
The patent resolves mutual interference by utilizing vertical stacking to separate adjacent electrodes in the third dimension. Positive and negative electrodes are arranged in alternating vertical layers, increasing the effective separation distance between adjacent electrodes while maintaining small lateral spacing. This dimensional separation reduces capacitive coupling and electromagnetic interference between electrodes, allowing miniaturization without compromising signal integrity.
Solution Approach 2:
The patent employs nested electrode stacking where multiple electrodes are arranged concentrically or in alternating layers within the same lateral footprint. This nested configuration increases the vertical separation between adjacent electrodes of opposite polarity, reducing mutual interference through three-dimensional spacing. The nested structure allows compact package size while maintaining adequate electrical isolation through vertical arrangement.
Data Source
AI summary
A semiconductor package includes a substrate including a core layer having a first surface and a second surface which is opposite to the first surface, a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer and exposed from the core layer and a second electrode disposed over the first surface, and a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed; a first semiconductor chip disposed over the first surface of the core layer; a second semiconductor chip stacked over the first semiconductor chip; a first connection member for connecting the first semiconductor chip with the first electrode; and a second connection member for connecting the second semiconductor chip with the second electrode.