Stepped Hard Mask Patterning for Semiconductor Memory Devices
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Solution Overview
Problem
The increasing complexity of semiconductor memory device fabrication due to the Double Patterning Technology (DPT) process, which requires multiple hard mask layers, makes it difficult to pattern cell and peripheral regions simultaneously, leading to increased mask numbers and process steps, and potential damage to one region during patterning of the other.
Innovation Solution
A method involving the formation of stepped hard mask structures with different etch barriers in the cell and peripheral regions, allowing for simultaneous patterning by using spacer patterns and hard mask layers with etching selectivity to reduce the total thickness of the hard mask structure and minimize process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If DPT process uses a plurality of hard mask layers for cell region patterning, then micro pattern formation precision is improved, but the total thickness of hard mask structure increases making peripheral region shallow junction formation difficult
Solution Approach 1:
The substrate is divided into cell region and peripheral region, with different hard mask layer configurations applied to each region. The cell region receives multiple hard mask layers for high-precision patterning, while the peripheral region uses fewer layers to maintain appropriate thickness for shallow junction formation.
Solution Approach 2:
Different regions of the substrate are assigned different hard mask layer structures tailored to their specific requirements. The cell region uses a complex multi-layer hard mask structure for micro pattern formation, while the peripheral region uses a simplified structure optimized for shallow junction formation, allowing each region to have optimal local properties.
2Manufacturing precision
If cell region and peripheral region are separately patterned, then each region can be optimized for its specific requirements, but the number of masks and process steps increases
Solution Approach 1:
The patterning processes for cell region and peripheral region are merged into a single integrated process sequence. By forming spacer patterns that serve dual purposes as both cell region etch barriers and peripheral region pattern definition elements, the invention reduces the total number of separate patterning operations while maintaining region-specific optimization.
Solution Approach 2:
The spacer patterns formed in the cell region serve multiple functions: they act as etch barriers for cell region patterning, define the boundaries for peripheral region processing, and protect underlying structures during subsequent etching steps. This multi-functionality reduces the need for separate dedicated structures for each region.
3Manufacturing precision
If one region is patterned first, then that region achieves its pattern, but the following patterning process may damage the already patterned region
Solution Approach 1:
Hard mask layers and spacer patterns are formed in advance to serve as protective barriers before subsequent patterning processes. These pre-formed structures cushion and protect already-patterned regions from damage during later etching and processing steps, ensuring that previously formed patterns remain intact throughout the fabrication sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient patterning of both cell and peripheral regions with reduced process complexity and cost, while ensuring micro pattern formation in the cell region and shallow junction formation in the peripheral region, thereby securing process margins.
Implementation Method 1
the second hard mask layer having an etching selectivity with the first hard mask layer
Implementation Method 2
the second hard mask layer having an etching selectivity with the first hard mask layer
Data Source
AI summary
A method for fabricating a semiconductor device includes forming an etch-target layer over a substrate having a first region and a second region, stacking first and second hard mask layers over the etch-target layer, forming spacer patterns over the second hard mask layer of the first area, etching the second hard mask layer using the spacer patterns as an etch barrier, forming a hard mask pattern over the first hard mask layer of the second region, etching the first hard mask layer using the second hard mask layer of the first region and the hard mask pattern of the second region as etch barriers, removing the hard mask pattern of the second region, and etching the etch-target layer using the first and second hard mask layers of the first region and the first hard mask layer of the second region as etch barriers.