Stepped Interposer for Hybrid Interconnect Geometry
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Solution Overview
Problem
Semiconductor packaging faces challenges in miniaturization and power density due to the need for varying interconnect sizes, particularly with large interconnect geometries like ball grid arrays (BGAs) that require larger sizes for maximum current carrying capacity, limiting footprint reduction and increasing interconnect density.
Innovation Solution
A stepped interposer design with recesses allows for interconnects of varying diameters, enabling larger interconnects in central zones for higher current carrying capacity and smaller interconnects near peripherals for increased input/output density, along with the integration of decoupling capacitors to improve power integrity and signaling performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large interconnect geometries like ball grid arrays (BGAs) are used to meet maximum current carrying capacity requirements, then power supply capability is improved, but package footprint size increases
Solution Approach 1:
The interposer implements different interconnect sizes at different locations: larger interconnects are positioned in central zones where high current carrying capacity is needed for power supply, while smaller interconnects are placed near peripherals for increased I/O density. This local differentiation resolves the contradiction by optimizing each region's interconnect size according to its specific functional requirements rather than using a uniform size throughout.
Solution Approach 2:
The patent introduces a stepped interposer design with varying thicknesses (different dimensions) to accommodate interconnects of varying diameters. By adding the vertical dimension through stepped structures and recesses, the design allows larger diameter interconnects to be positioned in thicker central regions while maintaining a compact overall footprint, thus resolving the contradiction between current carrying capacity and footprint size.
2Area of stationary object
If interconnect size is reduced to achieve footprint miniaturization, then package size is reduced, but current carrying capacity decreases
Solution Approach 1:
The interposer implements different interconnect sizes at different locations: larger interconnects are positioned in central zones where high current carrying capacity is needed for power supply, while smaller interconnects are placed near peripherals for increased I/O density. This local differentiation resolves the contradiction by optimizing each region's interconnect size according to its specific functional requirements rather than using a uniform size throughout.
3Ease of manufacture
If uniform interconnect size is used across the package, then manufacturing is simplified, but both power supply capability and I/O density cannot be optimized simultaneously
Solution Approach 1:
The interposer implements different interconnect sizes at different locations: larger interconnects are positioned in central zones where high current carrying capacity is needed for power supply, while smaller interconnects are placed near peripherals for increased I/O density. This local differentiation resolves the contradiction by optimizing each region's interconnect size according to its specific functional requirements rather than using a uniform size throughout.
Data Source
AI summary
An electronic device and associated methods are disclosed. In one example, the electronic device includes a substrate, a semiconductor die thereon, electrically coupled to the substrate, and an interposer adapted to connect the substrate to a circuit board. The interposer can include a major surface, a recess in the major surface, a first plurality of interconnects passing through the interposer within the recess to electrically couple the substrate to a circuit board, and a second plurality of interconnects on the major surface of the interposer to electrically couple the substrate to the circuit board, wherein each of the second plurality of interconnects comprises a smaller cross-section than some of the first plurality of interconnects.