Stepped Pad Structure for 3D Memory Contact Reliability
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Solution Overview
Problem
The challenge in manufacturing three-dimensional non-volatile memory devices is the difficulty in forming pad portions on stacked word lines and coupling contact plugs to these pad portions, often resulting in a punch phenomenon or failure of contact due to non-exposure of pad portions along the bottom surface of contact holes.
Innovation Solution
A semiconductor device with a substrate featuring alternately stacked conductive and insulating layers, where the ends of these stacked structures are patterned stepwise to expose thicker pad portions, allowing for increased thickness without height increase, and sacrificial layers are used to enhance contact plug formation and prevent etching issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pad portions are formed on stacked word lines in three-dimensional memory devices, then memory cell integration is improved, but manufacturing difficulty increases due to the complexity of forming contact plugs to exposed pad portions
Solution Approach 1:
The pad structure utilizes vertical stacking of multiple conductive layers to create pad portions with increased thickness in the vertical dimension. This dimensional change allows contact plugs to couple to pad portions more effectively, resolving the manufacturing difficulty while maintaining high memory cell integration.
Solution Approach 2:
The pad structure creates localized regions with different thicknesses - pad portions have greater thickness than unexposed portions of conductive layers. This local quality variation ensures reliable contact plug coupling at pad regions while maintaining the overall three-dimensional stacked structure for high integration.
2Reliability
If contact plugs are formed to couple to pad portions on stacked word lines, then electrical connection is improved, but punch phenomenon occurs causing manufacturing defects
Solution Approach 1:
By increasing pad portion thickness in the vertical dimension through stacked conductive layers, the target area for contact plug coupling is enlarged. This provides a larger margin for error during contact hole formation, preventing punch phenomenon while ensuring reliable electrical connection.
Solution Approach 2:
The pad structure is prepared in advance with sacrificial layers and stepped patterning to create exposed pad portions with greater thickness before contact plug formation. This preliminary preparation ensures that contact plugs can be reliably formed without punch defects.
3Reliability
If pad portions are exposed along the bottom surface of contact holes, then contact reliability is improved, but etching control becomes more difficult
Solution Approach 1:
The pad structure is segmented into multiple conductive layers separated by insulating layers, with sacrificial layers positioned strategically. This segmentation allows selective etching to expose pad portions at the bottom of contact holes while maintaining control over the etching process through the use of different material properties.
Solution Approach 2:
Sacrificial layers act as intermediaries during the etching process. These layers are removed selectively to expose pad portions, providing a controlled mechanism to achieve the desired exposure without direct difficulty in etching control. The sacrificial layers mediate between the etching process and the final pad exposure.
Data Source
AI summary
A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers.