Stepped Passivation Layer for Semiconductor Delamination

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Solution Overview

Problem

The existing semiconductor package formation processes face challenges with delamination issues between the passivation layer and the polymer planarization layer, which can lead to reliability concerns in the electrical connectivity and stability of the package.

Innovation Solution

A stepped passivation layer is formed with specific etching processes to create steps that reduce delamination, allowing for better stress distribution and increased resistance to interface delamination between the passivation layers, polymer planarization layer, and redistribution lines, enabling improved electrical connectivity through the formation of Under-Bump Metallurgy (UBM) and solder regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a planar passivation layer is formed over the redistribution line, then the manufacturing process is simple, but delamination occurs between the passivation layer and polymer planarization layer

Engineering Contradiction:
Improvepassivation layer formation processVSAvoidinterface delamination resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The passivation layer is segmented into multiple stepped levels instead of a single planar layer. The etching process creates first and second steps with different heights, dividing the originally uniform passivation layer into distinct segments that provide different mechanical properties and stress distribution zones, thereby preventing delamination while maintaining manufacturing feasibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the passivation layer are given different local qualities through the stepped structure. The first step region and second step region have different heights and stress characteristics, allowing each region to locally adapt to the underlying topography and reduce overall delamination stress at the interface

Inventive Principle:
Principle #3Local quality

2Length of stationary object

If the passivation layer is made thicker to improve coverage, then better protection is provided, but stress concentration increases leading to delamination

Engineering Contradiction:
Improvepassivation layer thicknessVSAvoiddelamination resistance
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The thick passivation layer is segmented into multiple stepped levels, where the first step has a first height and the second step has a second height. This segmentation distributes the stress that would otherwise concentrate in a uniformly thick layer, preventing delamination while maintaining adequate coverage and protection

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The passivation layer structure transitions from a two-dimensional planar configuration to a three-dimensional stepped configuration. By adding the vertical dimension with multiple height levels, the structure can better accommodate thermal and mechanical stresses without delaminating, effectively managing stress in an additional spatial dimension

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11450567B2Package component with stepped passivation layer
Publication Date: 2022.09.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11450567B2 patent drawing
  • US11450567B2 patent drawing
  • US11450567B2 patent drawing

AI summary

A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.