Stepped Via Design for Semiconductor Pad Electrode Thermal Stress
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Solution Overview
Problem
The existing semiconductor devices face issues with cracking and peeling due to differences in thermal expansion coefficients between the silicon substrate and the conductive layer, particularly during thermal processes like solder reflow or resin solidification, affecting the integrity of the pad electrode and adhesive layer.
Innovation Solution
A semiconductor device design featuring a semiconductor substrate with first and second openings of different diameters, where the second opening is smaller and reaches the pad electrode from the bottom of the first opening, covered with an insulating layer and a conductive layer, helps mitigate thermal expansion issues by reducing the diameter of the conductive layer and improving alignment precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a through hole is formed to electrically connect the pad electrode from the rear surface, then miniaturization of the solid-state imaging device is achieved, but cracking occurs on the silicon substrate due to thermal expansion difference between the silicon substrate and conductive layer
Solution Approach 1:
The through hole structure is segmented into multiple parts: a first opening extending from the rear surface, and a second opening formed at the bottom of the first opening to reach the pad electrode. This segmentation allows the conductive layer to be formed in a stepped configuration, reducing thermal stress concentration and preventing substrate cracking while maintaining electrical connectivity for miniaturization.
Solution Approach 2:
The conductive layer is formed with different configurations in different regions: in the first opening region, it follows the stepped structure to reduce stress, while in the second opening region near the pad electrode, it provides direct electrical connection. This local differentiation resolves the contradiction between miniaturization and substrate integrity.
2Ease of manufacture
If thermal process is applied for solidification of resin or reflow of solder, then packaging is completed, but peeling occurs at the interface between conductive layer and pad electrode due to thermal expansion
Solution Approach 1:
The stepped structure of the conductive layer is formed beforehand to compensate for thermal expansion forces that will occur during subsequent packaging processes. This pre-configured stress distribution prevents peeling at the conductive layer-pad electrode interface during resin solidification or solder reflow, ensuring reliable interface bonding while completing packaging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents cracking and peeling, enhances alignment precision, reduces parasitic capacitance, and improves handling and miniaturization capabilities, leading to higher reliability and reduced Turn Around Time (TAT) in manufacturing.
Implementation Method 1
an insulating layer formed to cover sidewall surfaces of the first opening and the second opening
Implementation Method 2
a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening
Data Source
AI summary
A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.