Stepwise Stacked Semiconductor Chips with Edge Bonding Pads
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Solution Overview
Problem
The semiconductor industry faces challenges in developing packaging technologies that enable high-density, reliable, and compact semiconductor devices with multiple stacked chips, as existing methods struggle to efficiently integrate and connect a large number of chips in a small area while maintaining effective electrical connections.
Innovation Solution
A semiconductor package design featuring stepwise-stacked chip structures with functional and dummy bonding pads on the edges, where functional pads occupy less than the entire edge region, allowing for efficient electrical connections and reduced package size through strategic placement and wire bonding, enabling effective electrical connectivity between chips and the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are vertically stacked to increase integration density, then the storage capacity and functionality are improved, but the package size and complexity increase
Solution Approach 1:
The patent transitions from horizontal chip arrangement to vertical stacking, utilizing the third dimension (height) to increase chip density. Multiple chip stacks are arranged vertically on the package substrate, allowing more chips to be integrated within the same footprint area, thereby improving storage capacity without proportionally increasing package volume.
Solution Approach 2:
The patent implements nested structures where chip stacks are positioned within the package substrate volume. Each chip stack consists of multiple chips stacked vertically, with lower stacks positioned beneath upper stacks. This nesting approach maximizes the use of available space within the package, allowing high-density integration while controlling overall package size.
2Quantity of substance
If the number of semiconductor chips in each package is increased to meet demands for large capacity, then the storage capacity is improved, but the manufacturing complexity and reliability challenges increase
Solution Approach 1:
The patent divides the package into multiple discrete chip stacks, where each stack is an independent unit comprising one or more semiconductor chips. This segmentation allows for modular manufacturing and assembly, where each stack can be prepared and tested separately before being integrated into the final package. The package substrate provides a common platform that organizes these segmented stacks in a systematic arrangement.
Solution Approach 2:
The package substrate serves multiple functions: it provides mechanical support for the chip stacks, establishes electrical connections between chips and external terminals, and organizes the spatial arrangement of stacks. The bonding pads on the substrate perform universal functions of electrical interconnection for all chip stacks, simplifying the overall packaging complexity despite the high number of chips integrated.
3Reliability
If functional bonding pads occupy the entire edge region of semiconductor chips, then the electrical connectivity is improved, but the available area for other structures is reduced
Solution Approach 1:
The patent applies local quality by concentrating functional bonding pads at specific locations (edge regions) of the semiconductor chips rather than distributing them uniformly across the entire chip surface. This localized arrangement ensures reliable electrical connections at critical interfaces while preserving chip area in other regions for active circuitry and other functional structures.
Solution Approach 2:
The package substrate acts as an intermediary between the chip stacks and the external environment. The substrate's bonding pads receive electrical connections from the chip edge regions and provide connections to external terminals, mediating the electrical interface. This allows the chips to have compact bonding pad arrangements while maintaining reliable electrical connectivity through the substrate's distribution network.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the integration density and reliability of semiconductor packages by reducing the occupied area, facilitating efficient wire bonding, and improving the yield of semiconductor products, thereby addressing the need for compact, high-capacity semiconductor devices.
Implementation Method 1
The functional bonding pads of the first chip stack are connected to the package substrate through the dummy pads of the second chip stack
Data Source
AI summary
A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, wherein each of the semiconductor chips includes a plurality of bonding pads provided on a respective edge region thereof, wherein at least some of the plurality of bonding pads are functional pads, and wherein the functional pads occupy a region that is substantially less than an entirety of the respective edge region.