STI Step Height Offset Control for Implant Critical Dimensions

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Solution Overview

Problem

Semiconductor processing faces significant variations in ion implant critical dimensions due to step heights in shallow trench isolation regions, leading to deleterious effects on device isolation and performance, especially as technology advances to smaller device sizes.

Innovation Solution

A method is introduced to improve critical dimensions by measuring and compensating for step heights using a modeled step height offset, which is integrated into the adaptive controller to determine the dosage of energy for photoresist patterning, thereby addressing the variability in implant dosages and critical dimensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If CMP polishing is performed to create planar surface, then surface flatness is improved, but step height variations at STI interfaces are generated due to differential polishing rates

Engineering Contradiction:
Improvesurface flatnessVSAvoidstep height control
Core Design Contradiction:
ShapeVSManufacturing precision

Solution Approach 1:

The patent measures the step height at the STI interface before photoresist patterning and uses this measurement to calculate a compensated exposure dosage. This preliminary measurement and compensation calculation enables the subsequent photoresist pattern to account for the step height variation, thereby controlling the implant critical dimension despite the stepped surface topology created by CMP polishing

Inventive Principle:
Principle #10Preliminary action

2Productivity

If photoresist patterning is performed without compensation, then patterning speed is maintained, but implant critical dimensions vary significantly due to step height effects

Engineering Contradiction:
Improvepatterning speedVSAvoidimplant critical dimension control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent implements a feedback mechanism where the measured step height from the STI interface is used to calculate a compensated exposure dosage for the photoresist patterning step. This feedback loop allows the system to adjust the patterning parameters based on actual surface conditions, thereby controlling the implant critical dimension while maintaining production efficiency

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the exposure dosage parameter of the photoresist patterning process based on the measured step height. By calculating a compensated dosage that accounts for the step height variation, the system adjusts the patterning parameter to achieve consistent implant critical dimensions despite variations in the underlying surface topology

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively controls and stabilizes ion implant critical dimensions, enhancing device performance and production yields by accounting for step height variations, leading to more precise patterning and improved semiconductor processing.

Implementation Method 1

a photoresist layer is formed over the semiconductor workpiece... the photoresist layer is patterned

Methodology Applied
Scientific EffectPhotolysis: Photodissociation

Data Source

PatentUS8530247B2Control of implant pattern critical dimensions using STI step height offset
Publication Date: 2013.09.10 TEXAS INSTRUMENTS INC
  • US8530247B2 patent drawing
  • US8530247B2 patent drawing
  • US8530247B2 patent drawing

AI summary

A method for semiconductor processing is provided, wherein a semiconductor wafer having undergone polishing is provided. The semiconductor wafer has an active region positioned between one or more moat regions, wherein the one or more moat regions have an oxide disposed therein. A top surface of the active region is recessed from a top surface of the moat region, therein defining a step having a step height associated therewith. A step height is measured, and a photoresist is formed over the semiconductor wafer. A modeled step height is further determined, wherein the modeled step height is based on the measured step height and a desired critical dimension of the photoresist. A dosage of energy is determined for patterning the photoresist, wherein the determination of the dosage of energy is based, at least in part, on the modeled step height. The photoresist is then patterned using the determined dosage of energy.