Stiffener Package Substrate Trace Width Modulation
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Solution Overview
Problem
Semiconductor packages with stiffeners experience performance issues due to signal interference and thickness challenges, as the stiffeners can cause crosstalk, insertion loss, and impedance mismatch when close to metal layers in the package substrate, necessitating additional shielding layers that increase thickness and manufacturing costs.
Innovation Solution
The implementation of a trace width modulation (TWM) technique on the package substrate, where conductive lines have varying widths under and outside the stiffener, and are perpendicular to its edges, to improve impedance matching and reduce the need for additional shielding layers, thereby minimizing signal interference and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a stiffener is placed close to metal layers in the package substrate, then mechanical stability against warpage and delamination is improved, but signal quality deteriorates due to crosstalk, insertion loss, and impedance mismatch
Solution Approach 1:
The patent applies local quality by making the conductive line width variable rather than uniform. The line width is locally adjusted in different regions: narrower under the stiffener where impedance needs to be higher, and wider outside the stiffener where impedance needs to be lower. This local variation in geometric property compensates for the local impedance changes caused by the stiffener's proximity, thereby maintaining consistent signal impedance and reducing signal interference while keeping the stiffener close to metal layers for mechanical stability.
2Object-generated harmful factors
If additional shielding layers are added to reduce signal interference from the stiffener, then signal quality is improved, but package thickness increases
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameter of the conductive line (width) to achieve impedance matching. Instead of adding more layers (increasing thickness), the invention changes the width parameter of existing conductive lines to compensate for impedance disruptions caused by the stiffener. This approach reduces signal interference through parameter optimization rather than structural addition, thereby maintaining thin package thickness while improving signal quality.
3Reliability
If additional shielding layers are added to shield the stiffener from signal routes, then electrical performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies local quality by implementing trace width modulation only in specific regions where conductive lines pass near or under the stiffener. Rather than adding complex shielding structures throughout the package, the invention locally modifies the conductive line geometry in problem areas. This targeted approach maintains electrical performance by addressing impedance issues only where needed, while keeping the overall manufacturing process simpler and more cost-effective compared to comprehensive shielding solutions.
Data Source
AI summary
Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.