Shallow Trench Isolation for CMOS Image Sensors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS image sensors face issues with increased peripheral capacitance and dark current due to shallow trench isolation regions, which also reduce the effective width of transistors and the fill factor of pixels.
Innovation Solution
The formation of shallow trench isolation regions with a dielectric structure, where the n-type isolation layer is only partially surrounding the photodetector and not the other electrical components, reducing capacitance and dark current while allowing for a wider photodetector and smaller transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation regions with n-type isolation layer are formed surrounding the photodetector and electrical components, then electrical isolation between pixels is achieved, but peripheral capacitance increases and dark current increases
Solution Approach 1:
The patent applies local quality by forming n-type isolation layers selectively only in specific regions where electrical isolation is most critical (around photodetectors and charge-to-voltage conversion regions) while omitting them in other areas. This localized approach maintains necessary electrical isolation while minimizing the generation of peripheral capacitance and dark current that would occur with complete surrounding isolation layers.
Solution Approach 2:
The isolation structure is segmented into discrete n-type isolation layers positioned at specific locations rather than forming continuous surrounding layers. The isolation layers are placed only where needed for electrical separation, breaking the continuous isolation structure into segmented portions that reduce harmful effects while maintaining isolation functionality.
2Reliability
If n-type isolation layer surrounds the photodetector and electrical components, then electrical isolation is achieved, but effective width of transistors is reduced
Solution Approach 1:
The patent uses local quality by positioning n-type isolation layers only in regions where electrical isolation is essential, thereby preserving transistor effective width in areas where isolation is not as critical. This selective placement ensures that transistor dimensions are not unnecessarily reduced while maintaining required isolation between adjacent pixels.
3Reliability
If n-type isolation layer is formed surrounding the photodetector, then electrical isolation is achieved, but fill factor of pixel is reduced
Solution Approach 1:
The isolation structure is segmented into discrete n-type layers positioned only where electrical isolation is most needed, rather than forming continuous surrounding isolation structures. This segmentation reduces the total area occupied by isolation features, thereby increasing the photodetector area and improving pixel fill factor while maintaining necessary electrical isolation.
Solution Approach 2:
By applying n-type isolation layers only in specific local regions where isolation is critical, the patent minimizes the overall area consumed by isolation structures. This localized approach preserves maximum photodetector area within the pixel, enhancing fill factor while providing adequate electrical isolation where required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces dark current and peripheral capacitance, increases the effective width of transistors, and enhances the fill factor of the pixel, leading to improved image sensor performance.
Implementation Method 1
Pixel 100 includes photodetector 102 that collects charge in response to incident light
Implementation Method 2
Shallow trench isolation regions (STI) surround the photodetector (PD) and the pixel 100 to electrically isolate the pixel from adjacent pixels in the image sensor
Data Source
AI summary
Shallow trench isolation regions are disposed in an n-type silicon semiconductor layer laterally adjacent to a collection region of a photodetector and laterally adjacent to a charge-to-voltage conversion region. The shallow trench isolation regions each include a trench disposed in the silicon semiconductor layer and a first dielectric structure disposed along an interior bottom and sidewalls of each trench. A second dielectric structure is disposed over the pinning layer. The dielectric structures include a silicon nitride layer disposed over an oxide layer. An n-type isolation layer is disposed along only a portion of the exterior bottom of the trench and the exterior sidewall of the trench immediately adjacent to the photodetector. The n-type isolation layer is not disposed along the remaining portion of the bottom or the opposing exterior sidewall of the trench.