Stitched Metal Zero Segments for Buried Power Routing
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Solution Overview
Problem
Advanced semiconductor integrated circuit (IC) manufacturing faces challenges in achieving uniformity and performance due to density gradient effects and landing effects associated with IC device layout configurations, which affect patterning and etching processes, necessitating adjustments in metal pattern placement and spacing to enhance device density and uniformity.
Innovation Solution
The implementation of a Litho-Spacer-Litho-Etch (LSLE) manufacturing sequence and two-dimensional AB color stitching methods to form stitched metal zero (M0) segments, allowing for improved signal routing flexibility by connecting M0 signal lines over buried power rails, using conductive materials like aluminum, copper, and cobalt, and employing EUV lithography for higher resolution and reduced photomask usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional metal patterning processes are used, then manufacturing simplicity is maintained, but density gradient effects and landing effects reduce manufacturing precision and device uniformity
Solution Approach 1:
The metal interconnect pattern is divided into multiple segments formed by different mask sets (first mask set for signal metal lines, second mask set for power metal lines). This segmentation allows independent optimization of each metal type's placement and spacing, enabling mitigation of density gradient effects and landing effects while maintaining overall pattern integrity and manufacturing precision.
2Manufacturing precision
If power metal pattern location and spacing are adjusted to mitigate DGE/LE effects, then manufacturing precision improves, but device complexity increases due to additional layout considerations
Solution Approach 1:
The interconnect pattern is segmented into signal metal lines and power metal lines formed by different mask sets, allowing independent optimization of each segment's placement to mitigate DGE/LE effects
Solution Approach 2:
The patent introduces a new dimension of control by using multiple mask sets (first and second mask sets) to form different metal patterns. This dimensional approach to pattern formation enables sophisticated placement strategies for power and signal metals without complicating the fundamental manufacturing process flow.
3Adaptability or versatility
If metal interconnect patterns are formed without segmentation, then ease of manufacture is maintained, but signal routing flexibility is limited due to inability to route over buried power rails
Solution Approach 1:
The metal interconnect pattern is divided into multiple segments formed by different mask sets (first mask set for signal metal lines, second mask set for power metal lines). This segmentation allows independent optimization of each metal type's placement and spacing, enabling mitigation of density gradient effects and landing effects while maintaining overall pattern integrity and manufacturing precision.
Solution Approach 2:
The patent introduces a new dimension of control by using multiple mask sets (first and second mask sets) to form different metal patterns. This dimensional approach to pattern formation enables sophisticated placement strategies for power and signal metals without complicating the fundamental manufacturing process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signal routing flexibility and improves the uniformity and performance of ICs by reducing processing time and increasing yield, while allowing for more complex and densely packed IC designs with better critical dimension uniformity.
Implementation Method 1
employing EUV lithography for higher resolution and reduced photomask usage
Data Source
AI summary
A method of designing a layout includes generating first routing tracks assigned to a first color group, generating second routing tracks assigned to a second color group, wherein a first routing track of the first routing tracks is between adjacent second routing tracks of the second routing tracks, and specifying a color stitching region connecting a selected first routing track of the first routing tracks with a selected second routing track of the second routing tracks of the layout, wherein the color stitching region represents a conductive region that connects a first conductive element represented by the selected first routing track with a second conductive element represented by the selected second routing track through an exposed portion of the selected first routing track, and wherein the exposed portion is at a removed portion of a sidewall structure surrounding the selected first routing track.


