ST-MRAM Storage Element Tunnel Barrier Layer Segmentation

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Solution Overview

Problem

The challenge in reducing power consumption and increasing capacity in Spin Torque Magnetic Random Access Memory (ST-MRAM) is exacerbated by the increase in magnetic interlayer coupling and defects due to the roughness of the tunnel barrier layer, which deteriorates the magnetoresistance ratio and read signal when the thickness of the tunnel barrier layer is decreased.

Innovation Solution

A storage element with a tunnel barrier layer thickness between 0.1 nm to 0.6 nm and interface roughness less than 0.5 nm is formed in multiple steps to minimize Neel coupling and defects, allowing for reduced resistance and power consumption without compromising the quality of the tunnel barrier layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the thickness of the tunnel barrier layer is decreased to reduce resistance and power consumption, then power consumption is reduced, but interface roughness increases causing increased Neel coupling and defects

Engineering Contradiction:
Improvepower consumptionVSAvoidinterface roughness
Core Design Contradiction:
Loss of energyVSManufacturing precision

Solution Approach 1:

The tunnel barrier layer formation process is divided into multiple sequential steps (first step and second step) to achieve the target thickness of 0.1 nm to 0.6 nm. This segmentation allows precise control of the thin film thickness while maintaining interface roughness below 0.5 nm, preventing excessive Neel coupling and defects that would otherwise occur with such thin layers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent optimizes the thickness parameter of the tunnel barrier layer to a specific range (0.1 nm to 0.6 nm) and controls the interface roughness parameter to be less than 0.5 nm. By precisely adjusting these parameters through multi-step formation, the patent achieves reduced resistance and power consumption while avoiding the harmful effects of interface roughness and Neel coupling.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the thickness of the tunnel barrier layer is decreased to reduce resistance, then resistance is reduced, but magnetic interlayer coupling increases due to roughness

Engineering Contradiction:
ImproveresistanceVSAvoidmagnetic interlayer coupling
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The tunnel barrier layer is formed in multiple steps rather than a single step, enabling precise thickness control at the atomic level (0.1 nm to 0.6 nm). This segmented approach ensures uniform thickness and smooth interfaces, preventing the magnetic interlayer coupling that would result from rough interfaces in thinner layers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent establishes optimal parameter ranges: tunnel barrier layer thickness of 0.1 nm to 0.6 nm and interface roughness less than 0.5 nm. These parameter optimizations simultaneously achieve low resistance while maintaining stable magnetic properties and preventing excessive interlayer coupling.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If the thickness of the tunnel barrier layer is decreased to improve power consumption, then power consumption is reduced, but defects increase due to roughness

Engineering Contradiction:
Improvepower consumptionVSAvoiddefects
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The multi-step formation process segments the thin film deposition into controlled stages, allowing each interface to form with minimal roughness. This segmentation prevents defect generation that would occur with single-step formation of such thin layers, maintaining high reliability while achieving low power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By optimizing the tunnel barrier layer thickness to 0.1 nm to 0.6 nm and controlling interface roughness to less than 0.5 nm, the patent achieves a parameter regime where low resistance (and thus low power consumption) is attained without introducing excessive defects or roughness-related reliability issues.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively decreases the resistance of the storage element, reduces power consumption, and maintains the quality of the tunnel barrier layer, thereby enhancing the performance and reliability of the ST-MRAM.

Implementation Method 1

A storage element by the spin torque magnetization reversal is configured with magnetic tunnel junction (MTJ) as with the MRAM. This configuration utilizes a characteristic that spin-polarized electrons passing through a magnetic layer pinned to a certain direction give torque to another magnetic layer that is free

Methodology Applied
Scientific EffectSpin torque magnetization reversal:

Implementation Method 2

The tunnel barrier layer has a thickness in the range from not less than or equal to 0.1 nm to not more than or equal to 0.6 nm and interface roughness less than 0.5 nm

Methodology Applied
Scientific EffectMagnetoresistance: Magnetoresistance

Data Source

PatentUS9472751B2Storage element, method for manufacturing storage element, and memory
Publication Date: 2016.10.18 SONY GROUP CORP
  • US9472751B2 patent drawing
  • US9472751B2 patent drawing
  • US9472751B2 patent drawing

AI summary

A method of manufacturing a storage element by forming a magnetic layer; and forming a tunnel barrier layer on the magnetic layer, wherein, n the forming a tunnel barrier layer, the tunnel barrier layer is formed to a predetermined thickness in at least two steps in a divided manner.