Stop-Etch Layer Interconnect Metallization for SiC Reliability
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Solution Overview
Problem
In semiconductor technology, particularly for power and RF devices using SiC and GaN, the coefficient of thermal expansion (CTE) mismatch between common interconnect metals like gold, aluminum, copper, and nickel, and semiconductor materials leads to metal failures due to thermal expansion, and existing metallization processes suffer from non-uniformity and machine/operator errors.
Innovation Solution
The use of a stop-etch layer, such as chrome, with interconnect metallization materials like titanium, titanium tungstate, titanium nitride, molybdenum, and tungsten, which have a CTE matched to the semiconductor material, along with a single lithographic step and metal mask formation to ensure uniform etching and protect underlying layers from etching agents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If common interconnect metals (gold, aluminum, copper, nickel) are used, then ease of manufacture is improved, but reliability deteriorates due to CTE mismatch with SiC and GaN semiconductor materials causing metal failures under thermal expansion
Solution Approach 1:
The patent employs a composite interconnect structure consisting of multiple metal layers with different properties. The first interconnect layer uses a CTE-matched metal (such as molybdenum, tungsten, or titanium) bonded directly to the SiC or GaN semiconductor to handle thermal expansion. Subsequent interconnect layers use conventional metals (gold, aluminum, copper, nickel) for electrical connectivity. This composite approach allows the system to achieve both reliability through CTE matching and ease of manufacture by using standard metals in upper layers.
2Device complexity
If prior-art etching methods are used, then device complexity is reduced, but manufacturing precision deteriorates due to non-uniformity across the wafer and machine/operator errors
Solution Approach 1:
The patent introduces a stop-etch layer as an intermediary between the CTE-matched first interconnect layer and the etching process. This stop-etch layer is selectively removed in patterned areas to expose the first interconnect layer for further processing, while protecting areas where the first interconnect layer should remain intact. This intermediary layer enables precise control over etching depth and prevents over-etching that would compromise the underlying CTE-matched metal, thereby improving manufacturing precision without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces thermally induced metal fatigue, ensures uniformity across the wafer/die, and safeguards against machine/operator errors, resulting in more reliable SiC and GaN-based semiconductor devices with improved fabrication processes.
Implementation Method 1
The interconnect metallization material may be etched from the non-resist-mask, the non-dielectric-mask, or the non-metal-mask covered areas, with the etching stopping at the stop-etch layer
Implementation Method 2
a lithography operation may etch dielectric deposited on top of the CTE matched interconnect metal layers, thereby forming a dielectric mask or pattern
Implementation Method 3
a stop-etch layer (e.g., chrome (Cr)) may be deposited over a wafer surface followed by the deposition of interconnect metallization material
Data Source
AI summary
Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method that includes depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a single lithography step to pattern a mask over the interconnect metallization material, etching the interconnect metallization material in non-masked areas, and removing the stop-etch layer. A system comprises a stop-etch layer material for deposit into a stop-etch layer over a wafer, an interconnect metallization material for deposit over the chrome layer, a lithography operation for patterning a mask over the interconnect metallization material, a first etching compound for etching the interconnect metallization material, where the etching stops at the stop-etch layer, and a second etching compound for removing the stop-etch layer.