Semiconductor Storage Clock Wiring to Reduce Data Timing Variation
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Solution Overview
Problem
As the speed of semiconductor storage devices increases, the reduced interval between data wiring lines leads to variations in data signal propagation due to capacitive coupling, narrowing the valid window for accurate clock signal adjustment and making it challenging to capture data signals effectively.
Innovation Solution
A semiconductor storage device with a control signal transmission circuit that generates multiple clock signals with different phases to synchronize data signal transmission, using first, second, and third clock wiring lines to ensure precise data capture by the sense amplifier, despite capacitive coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the interval between data wiring lines is reduced to increase the number of parallel data wiring lines, then the data transmission capacity is improved, but the propagation speed variation of data signals increases due to capacitive coupling
Solution Approach 1:
Shield wiring lines are introduced as intermediary elements between adjacent data wiring lines. These shield wiring lines act as mediators that intercept and redirect capacitive coupling effects, preventing direct interference between neighboring data lines. The shield lines are connected to ground potential, creating a reference plane that stabilizes the electromagnetic field distribution and reduces signal propagation variations.
Solution Approach 2:
The patent converts the harmful capacitive coupling effect into a beneficial phenomenon by intentionally introducing shield wiring lines that create controlled capacitive coupling. The shield lines, when connected to ground, transform the parasitic capacitance between data lines into a stabilizing effect that actually reduces propagation speed variation. The harmful coupling is redirected through the shield lines to achieve a positive outcome.
2Speed
If the propagation speed variation of data signals increases, then the width of the valid window for data capture is reduced, but the clock signal adjustment range required increases
Solution Approach 1:
Shield wiring lines serve as intermediary structures that decouple the capacitive interference between data wiring lines. By inserting these ground-referenced shield lines between adjacent data lines, the patent creates isolated transmission channels with stable propagation characteristics. This mediation reduces the variation in signal arrival times at the destination, thereby maintaining a sufficient valid window for reliable data capture without requiring extensive clock adjustment mechanisms.
3Object-affected harmful factors
If shield wiring lines are arranged between adjacent data wiring lines, then the capacitive coupling between data wiring lines is reduced, but the chip area increases
Solution Approach 1:
Instead of providing continuous shielding across the entire length of data wiring lines, the patent applies shielding selectively at critical locations where capacitive coupling has the most significant impact. The shield wiring lines are positioned between adjacent data lines at strategic intervals, providing localized protection against capacitive interference. This approach maintains effective coupling reduction while minimizing the additional chip area required compared to full-length shielding.
Solution Approach 2:
The patent implements partial shielding by placing shield wiring lines between only the most critical adjacent data wiring line pairs that exhibit excessive capacitive coupling, rather than shielding all possible combinations. This selective partial action achieves sufficient reduction of harmful coupling effects in the most problematic areas while avoiding the excessive area consumption that would result from comprehensive shielding of all data line interactions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for accurate capture of data signals by the sense amplifier, maintaining timing accuracy and reducing the need for large delay adjustment ranges or increased chip area, while minimizing capacitive coupling impacts.
Implementation Method 1
the propagation speed of the data signals varies due to capacitive coupling between the data wiring lines
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a sense amplifier, an input/output circuit, and a control signal transmission circuit. A first clock wiring line, a second clock wiring line extending along one side surface of the first clock wiring line, and a third clock wiring line extending along the other side surface of the first clock wiring line are connected to the control signal transmission circuit. The control signal transmission circuit outputs a first clock signal to the first clock wiring line, and outputs a second clock signal having a phase being reverse-phase to the first clock signal to the second clock wiring line and the third clock wiring line. A reception-side circuit captures the data signal in response to a delay clock signal output from a clock delay circuit.