Storage Controller Logical Partitioning and Port Allocation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current storage systems face bottlenecks in performance and reliability due to mechanical limitations in hard disk drives and inefficient use of bandwidth and processor throughput, especially when dealing with high-speed operations in SSDs, where data verification methods consume valuable transfer bandwidth and processor resources.

Innovation Solution

A storage system with a controller that logically partitions storage areas and allocates physical ports to these partitions, allowing for independent data transfer and verification using verification codes generated for each write block, thereby optimizing bandwidth usage and reducing processor load by only verifying data in specific blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data verification is performed by reading all written data and comparing byte-by-byte, then reliability is improved, but transfer bandwidth is consumed and processor throughput is reduced

Engineering Contradiction:
Improvedata verification reliabilityVSAvoidtransfer bandwidth utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts only the verification code from the written data for comparison purposes. Instead of reading and comparing all byte data, the system reads only the verification code portion appended to each data block, significantly reducing the amount of data transferred and processed while maintaining verification reliability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs partial verification by comparing only verification codes rather than complete data sets. This partial action approach provides sufficient reliability for most operations while consuming minimal bandwidth and processor resources, allowing the system to handle high-speed SSD operations efficiently

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If data verification is performed by reading all written data and comparing byte-by-byte, then reliability is improved, but processor throughput is reduced

Engineering Contradiction:
Improvedata verification reliabilityVSAvoidprocessor throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts only the verification code from the written data for comparison purposes. Instead of reading and comparing all byte data, the system reads only the verification code portion appended to each data block, significantly reducing the amount of data transferred and processed while maintaining verification reliability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical byte-by-byte comparison process with a more efficient verification code comparison mechanism. By using pre-computed verification codes (such as CRC or checksum values), the system substitutes intensive byte-level processing with lighter-weight code comparison operations, reducing processor throughput consumption

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Speed

If SSD is used to eliminate mechanical response time, then data read/write speed is improved, but interface configuration becomes a bottleneck

Engineering Contradiction:
Improvedata read/write speedVSAvoidinterface configuration complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments the interface bandwidth into multiple channels or lanes, allowing parallel data transfer operations. This segmentation enables the interface to handle high-speed SSD operations by distributing data flow across multiple pathways, preventing interface configuration from becoming a bottleneck

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from single-dimensional sequential data transfer to multi-dimensional parallel transfer by utilizing multiple interface lanes simultaneously. This dimensional change in data transfer approach allows the interface to keep pace with SSD speeds by operating in parallel rather than sequential mode

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Quantity of substance

If multiple LUs are placed in the same group, then storage capacity is improved, but access performance deteriorates due to physical access bottleneck

Engineering Contradiction:
Improvestorage capacityVSAvoidaccess performance
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent segments the storage system into multiple independent groups or pools, each with dedicated physical access pathways. By distributing logical units across these segmented groups rather than consolidating them in a single group, the system maintains high storage capacity while avoiding access bottlenecks through parallel physical access channels

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9710168B2Storage system
Publication Date: 2017.07.18 HITACHI VANTARA LTD
  • US9710168B2 patent drawing
  • US9710168B2 patent drawing
  • US9710168B2 patent drawing

AI summary

Disclosed is a storage system that suppress occurrence of a bottleneck in the storage system, efficiently uses a bandwidth of hardware, and achieves high reliability. A storage system includes a storage apparatus that stores data, a controller that controls data input/output with respect to the storage apparatus, and an interface that couples the storage apparatus and the controller. The storage apparatus has a plurality of physical ports that are couples to the interface. The controller logically partitions a storage area of the storage apparatus into a plurality of storage areas and provides the plurality of storage areas, or allocates the plurality of physical ports to the logically partitioned storage areas.