Storage Controller Read Latency Reduction via Mapping Table Overlap
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Solution Overview
Problem
Non-volatile data storage devices face increased read latency due to the need for Control Reads to retrieve logical-to-physical address mappings, especially when the mapping table is not cached, leading to reduced IOPS performance.
Innovation Solution
A data storage device controller initiates a first read operation to retrieve a representation of an entry from the logical mapping table and a second read operation to retrieve a codeword, decoding the codeword concurrently with a third read operation to retrieve data from the determined physical address, allowing for error correction and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Control Reads are issued to retrieve logical-to-physical address mappings from memory, then address mapping accuracy is improved, but read latency increases and IOPS performance deteriorates
Solution Approach 1:
The controller pre-loads portions of the logical-to-physical address mapping table into its local memory cache before they are needed. This preliminary action allows the controller to have the mapping information readily available without issuing Control Reads from the flash memory during actual data read operations, thereby reducing read latency while maintaining mapping accuracy.
Solution Approach 2:
The controller uses its local memory as an intermediary between the flash memory storage device and the host. Instead of directly reading from flash memory for each address mapping request, the controller first checks its local memory cache. This intermediary approach reduces the frequency of Control Reads to flash memory, decreasing overall read latency while maintaining accurate address mappings.
2Productivity
If the logical-to-physical address mapping table is stored entirely in the controller, then read performance is improved, but the controller memory requirement increases proportionally with storage capacity
Solution Approach 1:
The large logical-to-physical address mapping table is segmented into smaller portions that are loaded into the controller's local memory cache as needed. Rather than requiring the controller to store the entire mapping table, only the necessary portions are cached, allowing the controller to maintain fast read performance for accessed addresses while keeping memory requirements proportional to actual usage patterns rather than total storage capacity.
Data Source
AI summary
A data storage device includes a memory and a controller. The controller is configured to receive a read request that indicates a logical address. The controller is further configured to perform a first read operation to retrieve a representation of an entry of a logical mapping table from the memory, and perform a second read operation to retrieve a representation of a codeword from the memory. The controller is further configured to decode the representation of the codeword to determine whether an error exists at the entry, and, prior to completion of decoding, to initiate a third read operation to retrieve first read data from a first physical address corresponding to the logical address as determined based on the representation of the entry.