Storage Device Reference Clock Frequency Determination for Link Startup
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current storage systems face challenges in achieving high-speed linkup between hosts and storage devices, particularly in mobile devices, due to lengthy link startup processes that degrade performance.
Innovation Solution
Incorporating a reference clock pin and a reference clock frequency determination circuitry in the storage device to dynamically change speed gears based on the received reference clock frequency, enabling high-speed mode link startup and reducing linkup time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional link startup process is used between host and storage device, then the linkup process is simple, but the link startup time is lengthy and performance is degraded
Solution Approach 1:
The storage device performs preliminary actions by determining the reference clock frequency from the reference clock signal received through the reference clock pin before the link startup process begins. This allows the device controller circuitry to pre-configure the high speed mode link startup parameters, eliminating delays during the actual linkup process and reducing overall link startup time
Solution Approach 2:
The device controller circuitry dynamically adjusts the link startup process based on the determined reference clock frequency. The system transitions from a static, fixed-speed link startup to a dynamic process that adapts the speed gear and operational parameters according to the actual clock frequency detected, enabling optimized high-speed mode initialization
2Reliability
If the storage device waits for reference clock signal during initialization, then clock synchronization is achieved, but the booting time is increased
Solution Approach 1:
Instead of waiting passively for the reference clock signal during initialization, the storage device actively detects and determines the clock frequency as soon as the signal is available. The device controller circuitry rushes through the clock synchronization process by immediately performing frequency determination and configuring the high speed mode link startup, minimizing the booting time while ensuring reliable synchronization
Solution Approach 2:
The storage device performs self-service by autonomously determining the reference clock frequency from the received signal without requiring external configuration or manual intervention. The device controller circuitry automatically configures the high speed mode parameters based on the detected frequency, enabling the system to bootstrap itself quickly and reliably
Data Source
AI summary
A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.