Thin-Film Storage Transistor Band Engineering for Cool Electron Erase
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Solution Overview
Problem
Existing thin-film storage transistors face endurance issues due to programming window narrowing and degradation caused by hot holes generated during erase operations, which affect data retention and cycle longevity.
Innovation Solution
A storage transistor structure is designed with a tunnel dielectric layer and a charge-trapping layer having specific conduction band offsets, along with a barrier layer, to facilitate direct tunneling of 'cool electrons' during programming and erase operations, reducing energy loss and hot hole generation, thereby enhancing endurance beyond 10^11 cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If fast programming and erase operations are implemented using high current density, then programming and erase speed is improved, but device degradation and hot hole generation increase, reducing endurance
Solution Approach 1:
The patent changes the energy parameter of electrons by using a specific conduction band offset configuration in the charge-trapping layer. This allows electrons to tunnel with reduced energy loss, transforming high-energy electrons into low-energy electrons during erase operations, thereby reducing hot hole generation while maintaining fast erase speeds
Solution Approach 2:
The patent employs a composite dielectric structure consisting of a tunnel dielectric layer and a charge-trapping layer with specific materials (e.g., silicon nitride, silicon oxynitride) having tailored conduction band offsets. This composite structure enables selective electron tunneling with minimized energy loss, achieving both high speed and high endurance
2Speed
If high current density is used for fast erase operations, then erase speed is improved, but programming window narrowing occurs due to hot hole generation, worsening data retention
Solution Approach 1:
The patent modifies the energy parameter of electrons during erase operations by engineering the conduction band offset of the charge-trapping layer. This parameter change ensures that electrons lose minimal energy during tunneling, preventing hot hole generation that would otherwise cause programming window narrowing and data retention issues
Solution Approach 2:
The patent converts the potentially harmful high-energy electron tunneling process into a beneficial low-energy process by using the conduction band offset configuration. The charge-trapping layer acts as an energy filter, allowing electrons to tunnel efficiently while preventing the generation of harmful hot holes, thus protecting the programming window
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high endurance by maintaining a substantial direct tunneling current density while minimizing device degradation, ensuring reliable data retention and improved performance in quasi-volatile storage transistors.
Implementation Method 1
electrons direct tunnel into the charge-trapping layer
Data Source
AI summary
A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.