Strained Gate Electrodes for CMOS Carrier Mobility
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Solution Overview
Problem
Current CMOS manufacturing techniques face challenges in improving carrier mobility for both NMOS and PMOS devices without significantly increasing manufacturing complexity or cost, as NMOS requires biaxial tensile stress while PMOS requires compression stress, which existing methods struggle to achieve effectively.
Innovation Solution
The method involves forming a gate electrode layer with an amorphized portion and a cap layer to control crystal grain size and strain, allowing for selective stress introduction in semiconductor devices, optimizing both NMOS and PMOS transistors by varying the grain structure and stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If compression stress is applied to PMOS source/drain regions to improve PMOS carrier mobility, then PMOS performance improves, but additional processing steps and manufacturing complexity increase
Solution Approach 1:
The patent merges the stress introduction step with the existing source/drain formation process by forming SiGe layers during the same fabrication sequence. This integration allows compression stress to be applied to PMOS devices without adding separate processing steps, thereby improving PMOS carrier mobility while minimizing increases in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility by selectively controlling strain in semiconductor devices, improving performance without adding complexity or cost to the manufacturing process, effectively addressing the differing stress requirements of NMOS and PMOS devices.
Implementation Method 1
At least a portion of the gate electrode layer is amorphized, thereby creating an amorphized gate electrode layer
Implementation Method 2
at least a portion of the amorphized gate electrode layer is crystallized
Data Source
AI summary
Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.