Strained MOS Transistor Channels via Segmented Stressors
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Solution Overview
Problem
Conventional methods face difficulties in producing semiconductor integrated circuits with p-channel transistors under compressive strain and n-channel transistors under tensile strain simultaneously, which is essential for enhancing the performance of CMOS transistor pairs.
Innovation Solution
The solution involves a gate structure with a silicide stressor for p-channel transistors and a tensile capping layer for n-channel transistors, where the gate electrode of the n-channel transistor is over-etched to create a height difference, inducing longitudinal compressive stress in the p-channel and tensile stress in the n-channel, using a combination of silicide and capping layer to achieve the desired strain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-stress capping layer is used to create strain in the channel region, then the performance of the transistor is enhanced, but it is difficult to simultaneously provide both compressive strain for p-channel and tensile strain for n-channel transistors
Solution Approach 1:
The transistor structure is segmented into n-channel and p-channel regions, each with its own dedicated stressor mechanism. n-channel transistors use tensile capping layers while p-channel transistors use compressive silicide stressors, allowing independent strain optimization for each transistor type without interference
Solution Approach 2:
Different stressor types are applied to different local regions: tensile stress is applied locally to n-channel transistor channel regions via capping layers, while compressive stress is applied locally to p-channel transistor channel regions via silicide stressors on gate structures, enabling tailored strain for each transistor type
2Reliability
If silicide stressors are used on the gate structure to create compressive strain, then p-channel transistor performance is enhanced, but it is difficult to simultaneously achieve tensile strain in n-channel transistors
Solution Approach 1:
The stressor system is segmented into two independent components: silicide stressors for p-channel transistors and capping layers for n-channel transistors. This segmentation allows each stressor type to be optimized for its intended transistor type without compromising the other
Solution Approach 2:
The gate structure serves as an intermediary element that can incorporate silicide stressors for p-channel transistors, while the overlying capping layer acts as a mediator that provides tensile strain for n-channel transistors, enabling both strain types through the same overall structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively optimizes the performance of both n-channel and p-channel transistors by precisely controlling the strain in their channel regions, enhancing their operational efficiency.
Implementation Method 1
A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor
Implementation Method 2
a gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor
Data Source
AI summary
The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor.