Strained Nanosheet Channel Structure for Higher MOSFET Mobility

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Solution Overview

Problem

As semiconductor devices continue to scale, stress engineering from external stressors becomes increasingly challenging, and it is difficult to provide strain for an Si channel to achieve high mobility for carrier transport in MOSFETs.

Innovation Solution

A strained channel is utilized, comprising a silicon germanium core layer and a silicon cladding layer disposed on the core layer, to efficiently generate channel strain and enhance carrier transport mobility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional planar FET fabrication techniques are used, then manufacturing simplicity is maintained, but device density and performance are limited

Engineering Contradiction:
Improvedevice densityVSAvoidfabrication complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The channel is segmented into multiple nanosheet layers stacked vertically, transforming the conventional planar channel into a three-dimensional stacked structure. This segmentation enables increased device density by utilizing the vertical dimension while maintaining compatibility with existing fabrication processes through modular construction approaches.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a two-dimensional planar channel to a three-dimensional stacked nanosheet architecture. By adding the vertical dimension with multiple spaced-apart nanosheet layers, the device achieves higher density and improved gate control without fundamentally complicating the fabrication workflow.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If external stressors are applied for strain engineering in scaled devices, then carrier mobility can be enhanced, but fabrication complexity and difficulty increase

Engineering Contradiction:
Improvecarrier transport mobilityVSAvoidstress engineering complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The channel structure uses composite materials consisting of silicon germanium core layers and silicon cladding layers. This material composition generates intrinsic strain through lattice mismatch between the different semiconductor materials, eliminating the need for external stressors while enhancing carrier mobility in the silicon channel regions.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The strained silicon channel is localized within specific regions of the nanosheet structure, with strain generated only where needed in the silicon core layers. The silicon germanium/silicon composite structure creates localized strain fields that improve carrier transport exactly where required, without affecting the entire device uniformly or requiring global stress engineering.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The strained channel effectively improves carrier transport mobility by providing necessary strain, addressing the challenges of scaling in semiconductor devices.

Implementation Method 1

A strained channel is utilized, comprising a silicon germanium core layer and a silicon cladding layer disposed on the core layer, to efficiently generate channel strain and enhance carrier transport mobility

Methodology Applied
Scientific EffectStrain: Deformation

Data Source

PatentUS20240170538A1Semiconductor structure with strained nanosheet channel
Publication Date: 2024.05.23 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20240170538A1 patent drawing
  • US20240170538A1 patent drawing
  • US20240170538A1 patent drawing

AI summary

A semiconductor structure includes a field-effect transistor region having a strained channel. The strained channel has a silicon germanium core layer and a silicon cladding layer disposed on the core layer.