Strained Nanowire CMOS Transistors on Single Substrate

Solution Overview

Problem

Current semiconductor nanowire technologies either use unstrained materials or only one strained material for both nFET and pFET devices, limiting the performance enhancement of CMOS devices, as tensile strained silicon nanowires are beneficial for nFETs but not for pFETs, and vice versa.

Innovation Solution

A method and structure that enable tensile strained silicon nanowires in the nFET device region and compressively strained silicon germanium alloy (SiGe) nanowires in the pFET device region on the same substrate, using a material stack with alternating layers of strained silicon and SiGe, patterned to form nanowire stacks within specific device regions, with gate structures formed over these nanowires to maintain strain.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If tensile strained silicon nanowires are used in nFET devices, then drive current is improved, but pFET devices cannot benefit from strain

Engineering Contradiction:

Improvedrive currentVSAvoidcompatibility with both nFET and pFET

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent applies local quality by implementing different strain types in different spatial locations: tensile strained silicon nanowires are formed in the nFET device region while compressively strained SiGe nanowires are formed in the pFET device region. This is achieved through a material stack with alternating layers of strained silicon and SiGe that are selectively patterned and suspended in different device regions, allowing each transistor type to receive the appropriate strain for optimal performance

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the substrate into distinct nFET device regions and pFET device regions, with each region receiving a different strained nanowire material. The material stack is divided into alternating layers that are selectively processed in different regions, enabling independent optimization of nFET and pFET devices on the same substrate

Inventive Principle:

Principle #1Segmentation

2Productivity

If compressively strained SiGe nanowires are used in pFET devices, then drive current is improved, but nFET devices cannot benefit from strain

Engineering Contradiction:

Improvedrive currentVSAvoidcompatibility with both nFET and pFET

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent applies local quality by implementing different strain types in different spatial locations: tensile strained silicon nanowires are formed in the nFET device region while compressively strained SiGe nanowires are formed in the pFET device region. This is achieved through a material stack with alternating layers of strained silicon and SiGe that are selectively patterned and suspended in different device regions, allowing each transistor type to receive the appropriate strain for optimal performance

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the substrate into distinct nFET device regions and pFET device regions, with each region receiving a different strained nanowire material. The material stack is divided into alternating layers that are selectively processed in different regions, enabling independent optimization of nFET and pFET devices on the same substrate

Inventive Principle:

Principle #1Segmentation

3Ease of manufacture

If all nanowire structures use unstrained or single strained material, then manufacturing is simplified, but CMOS performance cannot be fully optimized

Engineering Contradiction:

Improvenanowire structure uniformityVSAvoidCMOS device performance

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent employs composite materials by creating a material stack with alternating layers of strained silicon and SiGe, where each material provides different mechanical properties. The strained silicon layers provide tensile strain for nFET regions while the SiGe layers provide compressive strain for pFET regions. This composite structure enables both types of strained nanowires to coexist on the same substrate through selective suspension and patterning

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The patent applies local quality by implementing different strain types in different spatial locations: tensile strained silicon nanowires are formed in the nFET device region while compressively strained SiGe nanowires are formed in the pFET device region. This is achieved through a material stack with alternating layers of strained silicon and SiGe that are selectively patterned and suspended in different device regions, allowing each transistor type to receive the appropriate strain for optimal performance

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10079303B2Method to form strained nFET and strained pFET nanowires on a same substrate

Publication Date: 2018.09.18 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A semiconductor is provided that includes an nFET gate structure straddling over a first nanowire stack and a portion of a first SiGe layer having a first Ge content. The first nanowire stack comprises alternating layers of a tensily strained silicon layer, and a second SiGe layer having a second Ge content that is greater than the first Ge content and being compressively strained. Portions of the tensily strained silicon layers extend beyond sidewalls surfaces of the nFET gate structure and are suspended. The structure further includes a pFET gate structure straddling over a second nanowire stack and another portion of the first SiGe layer. The second nanowire stack comprises alternating layers of the tensily strained silicon layer, and the second SiGe layer. Portions of the second SiGe layers extend beyond sidewalls surfaces of the pFET gate structure and are suspended.