Compressively-Strained Silicon Layer via Crystalline Bridge
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Solution Overview
Problem
Current semiconductor technologies face challenges in enhancing hole mobility in p-channel CMOS transistors, as existing strained silicon germanium layers require expensive processes and do not efficiently introduce compressive strain for improved performance.
Innovation Solution
A method involving the formation of a compressively-strained silicon layer by bonding a bowed ultrathin silicon film onto a silicon substrate, using a crystalline semiconductor bridge with a middle portion separated from the substrate to introduce compressive strain, achieving a strain range of 0.2% to 1.0% and a thickness of 10 nm to 20 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If strained silicon germanium layers are used to enhance hole mobility in p-channel CMOS transistors, then hole mobility is improved, but the manufacturing cost increases due to expensive ultra high vacuum chemical vapor deposition processes
Solution Approach 1:
The patent replaces expensive UHVCVD processes with a cheaper ion implantation method followed by solid phase epitaxial regrowth. The strained silicon layer is formed through a lower cost process sequence that achieves the same functional result of enhancing hole mobility without requiring expensive ultra high vacuum equipment
Solution Approach 2:
The patent substitutes the mechanical/chemical vapor deposition process with an ion implantation process followed by thermal regrowth. Instead of depositing silicon germanium through complex CVD machinery, the method uses ion implantation to create a damaged layer that is then regrown in-situ, replacing expensive mechanical deposition systems with simpler ion beam and thermal processing equipment
2Stability of the object's composition
If germanium content is graded in steps to form a fully relaxed silicon germanium buffer layer, then strain is reduced and layer stability is improved, but the manufacturing complexity and process time increase
Solution Approach 1:
The patent performs preliminary damage creation through ion implantation before the regrowth step. The ion implantation pre-configures the silicon layer with a controlled damaged region that will become the strained silicon layer after regrowth, eliminating the need for time-consuming graded buffering and enabling direct formation of the functional strained layer
Solution Approach 2:
The patent extracts and removes the time-consuming graded buffering step from the process sequence. By using ion implantation followed by direct solid phase epitaxial regrowth, the method eliminates the intermediate graded silicon germanium buffer layers that would otherwise be required to gradually relax strain, significantly reducing total process time while maintaining layer quality
3Speed
If thin strained silicon layers are used to improve carrier mobility, then device speed is enhanced, but the lattice mismatch tolerance decreases and manufacturing precision requirements increase
Solution Approach 1:
The patent changes the physical state and structural parameters of the silicon layer through ion implantation damage and controlled thermal regrowth. By modifying the crystal structure through radiation damage and then regrowing it in-situ, the method achieves precise lattice matching and strain control that is more difficult to obtain through conventional thin film deposition, even for very thin layers
Solution Approach 2:
The patent uses the original silicon substrate as a template or copy source for regrowing the strained silicon layer. The solid phase epitaxial regrowth process copies the crystal structure from the undamaged substrate regions to the damaged regions, ensuring precise lattice matching and reducing manufacturing precision requirements compared to depositing entirely new thin layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves hole mobility in p-channel transistors, leading to enhanced PMOS drive current and more symmetrical switching characteristics compared to NMOS devices, resulting in improved CMOS circuit performance.
Implementation Method 1
The middle portion of the bridge is bonded to the substrate to provide a strained semiconductor layer on the substrate. The strained semiconductor layer has enhanced carrier mobility due to the strain.
Implementation Method 2
The crystalline silicon layer is strained by a lattice mismatch between the silicon germanium layer and the crystalline silicon layer.
Implementation Method 3
bonding a compressively-strained silicon layer to a silicon substrate in local areas. Some embodiments form the compressively-strained silicon layer by bowing an ultrathin silicon film over the surface of a silicon wafer, and bonding the silicon film onto the flat wafer
Implementation Method 4
The substrate is heat treated to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process.
Data Source
AI summary
One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein.