Strained Silicon Metal Gate Transistor Threshold Voltage Control

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Solution Overview

Problem

High-k metal gate (HKMG) transistors face challenges in achieving ideal threshold voltage due to limited availability of thermally stable metal gate materials with appropriate work-function matching the silicon substrate, and the use of dipole layers often degrades electron mobility.

Innovation Solution

The semiconductor structure incorporates a strained silicon layer with biaxial tensile strain for n-type FETs and a silicon-germanium layer with high Ge content for p-type FETs, separated by shallow trench isolation, to reduce threshold voltage and minimize dipole layer thickness, thereby improving electron mobility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If suitable metal gate material is used to match work-function, then threshold voltage control improves, but material availability is limited

Engineering Contradiction:

Improvethreshold voltage controlVSAvoidmetal gate material availability

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent changes the approach from selecting different metal gate materials to controlling the electrical characteristics through strain engineering of the silicon channel. By adjusting the buffer layer parameters, the threshold voltage can be tuned without being constrained by the limited availability of metals with specific work-functions

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies strain locally to the channel region through the relaxed buffer layer, creating a localized modification of the silicon crystal structure. This local quality change enables threshold voltage control specifically in the active device region without requiring changes to the gate material properties

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively lowers the threshold voltage of HKMG transistors by approximately 100-350 mV and reduces the need for thicker dipole layers, minimizing electron mobility degradation.

Implementation Method 1

an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, the strained silicon layer being formed directly on top of a layer of insulating material

Methodology Applied

Scientific EffectBiaxial tensile strain: Deformation

Implementation Method 2

a p-type field-effect-transistor (PFET) being formed on top of the stained silicon layer via a layer of silicon-germanium (SiGe)

Methodology Applied

Scientific EffectSilicon-germanium alloying: Composite Materials

Data Source

PatentUS8643061B2Structure of high-K metal gate semiconductor transistor

Publication Date: 2014.02.04 GLOBALFOUNDRIES US INC

AI summary

A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.