Strained SOI Active Regions for Transistor Scaling
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Solution Overview
Problem
The challenge in integrated circuit manufacturing is to maintain a high strain component in transistor channel regions as device dimensions shrink, leading to reduced controllability and increased leakage currents, while existing strain-inducing mechanisms are limited in scalability and flexibility.
Innovation Solution
The technique involves forming trench isolation structures in a globally strained semiconductor layer, allowing for adaptive strain management by adjusting the layer thickness based on patterning requirements, which helps maintain a significant strain component even as device dimensions reduce, enabling efficient strain induction and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of the semiconductor layer is reduced to improve device scaling and reduce leakage currents, then the charge carrier mobility enhancement through strain is diminished due to strain relaxation
Solution Approach 1:
The patent changes the physical state of the semiconductor layer by introducing biaxial strain through a lattice-mismatched buffer layer (e.g., SiGe buffer for Si channel). This parameter change (adding strain) compensates for the strain relaxation that occurs when reducing layer thickness, thereby maintaining charge carrier mobility enhancement even in scaled devices
Solution Approach 2:
The patent uses a composite structure consisting of a strained semiconductor layer grown on a buffer layer with different lattice constant (e.g., Si/SiGe). This composite material system allows the thin semiconductor layer to maintain high strain levels because the buffer layer provides continuous strain support, preventing strain relaxation that would occur in standalone thin layers
2Reliability
If additional strain-inducing mechanisms are introduced to maintain strain in scaled devices, then the process complexity and number of process steps increase
Solution Approach 1:
The patent applies preliminary action by introducing strain during the epitaxial growth of the semiconductor layer itself, rather than adding strain afterward through separate process steps. The strained layer is formed in-situ during the initial layer deposition, combining the thinning and strain induction into a single integrated process
Solution Approach 2:
The epitaxial growth process serves multiple functions simultaneously: it forms the thin semiconductor layer for device scaling and introduces biaxial strain for mobility enhancement in the same process step. This multi-functional approach avoids the need for separate strain-inducing mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains a high strain component in transistor channel regions, enhancing charge carrier mobility and performance, while reducing the complexity of additional process steps and maintaining scalability, thus addressing the limitations of existing strain-inducing mechanisms.
Implementation Method 1
a silicon-containing semiconductor layer above a substrate, wherein the silicon-containing semiconductor layer has an internal biaxial strain
Implementation Method 2
The isolation trenches are filled with an insulating material
Data Source
AI summary
In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strain component. The active regions of reduced height may be advantageously used for forming fully depleted field effect transistors.