Strained SOI Substrate Using Trench Isolation for Carrier Mobility
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Solution Overview
Problem
Conventional strain liners become ineffective at tight pitches as semiconductor devices scale with future technology nodes, and the manufacturing of strained SOI substrates using thick, relaxed silicon germanium epitaxy is not cost-effective.
Innovation Solution
A method involving a lattice-matched second semiconductor layer subjected to directional stress, with trench isolation structures formed through the active device and second semiconductor layer to relax the strain and impart opposite stress on the active device layer, using a thin SiGe layer under buried oxide to apply strain to the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick, relaxed silicon germanium epitaxy is used to create strained SOI substrates, then carrier mobility is enhanced, but manufacturing cost increases significantly
Solution Approach 1:
The patent changes the thickness parameter of the SiGe layer from thick (conventional) to thin (50-200 nm), and changes the stress state parameter from relaxed to strained through the formation of trenches. This transforms the manufacturing approach from costly thick epitaxy to a more efficient thin-film strain engineering process that achieves the same carrier mobility enhancement at lower cost.
Solution Approach 2:
The patent applies strain locally to the channel region by forming trenches specifically in the SiGe layer beneath the active device area. This localized strain application through trenches creates the necessary stress in the channel to enhance carrier mobility, while avoiding the need for expensive thick SiGe epitaxy across the entire wafer.
2Productivity
If conventional strain liners are used, then device drive current is enhanced, but effectiveness is lost at tight pitches
Solution Approach 1:
The patent transitions from planar strain liners (2D approach) to a 3D strain engineering approach using trenches that extend vertically through the SiGe layer. This dimensional change allows strain to be applied effectively even at tight pitches where conventional planar liners become ineffective, maintaining device drive current enhancement in scaled technologies.
3Ease of manufacture
If a thin SiGe layer is used under buried oxide, then manufacturing cost is reduced, but strain transfer to the channel must be optimized
Solution Approach 1:
The patent segments the SiGe layer by forming trenches that divide it into isolated regions. This segmentation serves dual purposes: it releases misfit dislocations to prevent defects while simultaneously applying compressive strain to the overlying channel. The trench geometry and depth are precisely controlled to optimize strain transfer efficiency from the thin SiGe layer to the channel, achieving both cost reduction and high manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach efficiently transfers strain to the channel, enhancing carrier mobility and circuit performance without increasing device size or capacitance, while being cost-effective by using a thin semiconductor layer.
Implementation Method 1
the second semiconductor layer is lattice matched to the first semiconductor substrate such that the second semiconductor layer is subjected to a first directional stress
Implementation Method 2
forming one or more trench isolation structures through the active device layer and through the second semiconductor layer so as to relax the second semiconductor layer below the active device layer and impart a second directional stress on the active device layer opposite the first directional stress
Data Source
AI summary
A method of forming a strained, semiconductor-on-insulator substrate includes forming a second semiconductor layer on a first semiconductor substrate. The second semiconductor is lattice matched to the first semiconductor substrate such that the second semiconductor layer is subjected to a first directional stress. An active device semiconductor layer is formed over the second semiconductor layer such that the active device semiconductor layer is initially in a relaxed state. One or more trench isolation structures are formed through the active device layer and through the second semiconductor layer so as to relax the second semiconductor layer below the active device layer and impart a second directional stress on the active device layer opposite the first directional stress.